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CMOS logic gate simulation using a physically-derived large-signal nonquasi-static MOSFET model

Posted on:2009-07-10Degree:M.S.EType:Thesis
University:The University of Alabama in HuntsvilleCandidate:Palanichamy, ChandraFull Text:PDF
GTID:2448390005956796Subject:Engineering
Abstract/Summary:
This thesis presents a CMOS logic gate simulation using a physically-derived large-signal, nonquasi-static model for the transient analysis of MOSFET devices and circuits. The nonquasi-static model is implemented within a high-level language and the interactive environment of MATLABRTM for the numerical simulation of individual MOSFET devices and CMOS logic circuits. This work extends the nonquasi-static model for a four input CMOS NOR and NAND gate. Euler's method is used in the calculation of the output voltage of each CMOS logic circuit, and a bisection root finding algorithm is used for calculation of junction voltages.;The implemented model calculates the transient terminal currents and voltages of individual MOSFET devices, while providing voltage transfer curves, load capacitance, load current and switching speeds for the CMOS logic circuits. Results are compared with those obtained from SPICE Level 3 model.
Keywords/Search Tags:CMOS logic, Physically-derived large-signal, MOSFET
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