Modeling and simulation of the fully depleted silicon-on-insulator MOSFET for submicron CMOS IC design

This dissertation concerns physical modeling and simulation of the fully depleted silicon-on-insulator (SOI) MOS field-effect transistor (MOSFET) for submicron complementary-MOS (CMOS) integrated circuit (IC) design. Design issues are studied, focusing on the hot-carrier-related device degradation and the floating-body effects, which are the main concerns regarding the contemporary scaled technology. The hot-carrier-related device degradation is monitored by the impact-ionization current in the MOSFET, and a moderate (not ultra-thin) SOI film thickness is suggested to reduce the high drain field that underlies the degradation. Floating-body effects, which are difficult to characterize by measurements, are intensively analyzed through numerical device simulations. The off-state latch resulting from activation of the parasitic bipolar junction transistor (BJT) is found to be most detrimental to circuit performance, and a lightly doped source (LDS) structure is suggested to limit the BJT current gain and suppress the latch. A new model for the fully depleted SOI MOSFET that accounts for the important features, including the subthreshold conduction, the parasitic BJT effects, the effects of the LDS and the lightly doped drain (LDD), and the thermal generation current, is developed. The model is physical, requiring semi-numerical analyses, and therefore is applicable to devices having any channel length for any SOI film thickness, so long as the full-depeletion assumption is valid. The model is implemented in the source code of the circuit simulator SPICE2 to create SOISPICE-2, a semi-numerical device/circuit simulator, which can be effectively used as a design tool for thin-film SOI CMOS ICs. The detailed model algorithm and numerical techniques chosen to increase the computational efficiency and to alleviate convergence problems of SOISPICE-2 are described. DC simulations for half-micron thin-film SOI MOSFETs are compared with corresponding measurements and numerical device simulations done with PISCES to provide some support for the model. The utility and the efficiency of SOISPICE-2 are demonstrated through representative device and circuit simulations.