Research On Non-linear Modeling Technique For CMOS Transistor

With the rapid development of 5^th-Generation Mobile Communication Technology(5G),Internet of Things(Io T),cloud cumputing and automotive electronics,the application prospects of radio frequency integrated circuit(RFIC)is bright.Benefit from low cost,low power consumption,high integration density,high reliability and so on,mature CMOS technology has been widespreadly used in RF chip design.The device model serves as a bridge between manufacturing and circuit design,it plays an important role in the samulation stage of circuit design.The precision and sumulation effciency of the model not only directly determine the cost of chip development,but also have have guiding significance to the iteration and upgrade of semiconductor process and circuit design,as a result,transistor modeling has attracted great attention in academia and industry.In order to meet market demand,the cut-off frequency of CMOS transistor continues to rise,the process nodes are shinking,and the feature size of CMOS transistor is becoming smaller and smaller.With the decrease of process node,some nonlinear phenomena and high frequency parasitic effects caused by manufacturing become nonnegligible,which requires constant updating of the transistor model to accurately describe these effects.Based on 180-nm SOI MOSFET process,a series of studies on transistors'non-linear characteristics have been done in this work.Firstly,this article elaborates the physical structure and working principle of MOSFET.Then,the SOI MOSFET process and its basic physical effects have been introduced.Besides,a brief describtion of the on-chip measurement and transistor de-embedding method is provided.Secondly,a small-signal equivalent circuit model for SOI MOSFET is established and the parameters of intrinsic part are extracted.The accuracy of this model is verified from 1GHz to 60GHz,under multiple bias conditions.Then,based on the small-signal model,the noise model of the transistor is finished.On the basis of Van der Ziel's classical noise model,considering the frequency dispersion effect of the gate induced noise,a frequency dispersion factor was added to the clasical model expression and Taylor expansion was carried out to obtain the improved noise model.Noise parameters and noise circle's simulation results and measurement results are used to verify the accuracy of the model.Thirdly,by taking the Kink effect and self-heating effect into consideration,the nonlinear current model of SOI MOSFET is established and verified.Based on that,the compression phenomenon of gate-source parasitic capacitance when the transistor is operating in the triode region is investigated,by adding a hyperbolic tangent function to the traditional capacirance model,the accuracy of the model is significantly improved.Finally,on the basis of the above work,transistor's large-signal equivalent circuit model is established.The performance of the large signal model in the output power,gain and additional power efficiency is verified by power sweep measurement,which achieves high precision.This work is of great significance for improving the accuracy of the existing SOI MOSFET model and analyzing the high frequency effects of transistors.