A multi-level simultaneous bidirectional I/O for high speed applications

The trend in VLSI has been toward higher performance and integration at the expense of higher power dissipation and circuit complexity. This increase in circuit complexity raises the need for high speed communication with the external devices for storage, display, or data processing. Also, the longer word size and the higher data rate in the chip interface lead to an increase in the number of I/O pins in a unit area of a package and the power dissipation. To mitigate this increase in circuit complexity, geometries have been aggressively scaled down.;In chip-to-chip communications, the topology of the communication affects the performance of the communication links. Multidrop is a configuration in which components are all connected to the same set of communication wires. It polls data in sequence over one communication wire which results in a cheaper solution at the expense of response time. A point-to-point link dedicates one communication line between two chips. It is usually preferred for the high speed links that require high reliability. In a point-to-point link, increasing the symbol rate per wire enhances data rate per wire. Simultaneous Bidirectional (SBD) signaling was introduced to allow simultaneous data transmission in two directions over one wire, doubling the effective data rate over a point-to-point unidirectional transmission. The N-bit SBD I/O enhances data rate over SBD I/O by a factor of N at the expense of smaller voltage window.;This thesis describes a high speed multi-level simultaneous bidirectional I/O. When I/Os switch data in the same direction simultaneously, they consumed large current to drive the output loads, which causes simultaneous switching noise (SSN) induced by parasitics. A differential scheme that reduces the total sum of AC currents is applied at the expense of static current flow. To increase data rate, first, calibration is considered for the impedance mismatch between chips which reduces the voltage margin. Additionally a band-gap reference is used to reduce the effects of supply voltage fluctuation, temperature variation, and chip-to-chip mismatches. Secondly, in an I/O, larger switching currents limit the bandwidth because of this a latched differential current switching scheme and pre-emphasis are applied to enhance the speed in the transmitter. In the receiver, a pre-distorted version of its own transmit data is subtracted by using de-emphasis in the reference voltages. A clocked comparator with pre-charge for the higher symbol rate.;In the receiver end, a voltage references with de-emphasis to match the received signal through channel distortion and a clocked comparator with pre-charge are applied for the higher symbol rate. Simulation results based on a 0.18m CMOS process show that the proposed I/O achieves a data rate up to 8-Gb/s/pin with the power consumption of 46.8mW for 1.8V power supply. Measurement data is presented, analyzed, and discussed.