Research And Implementation Of Simultaneous Bidirectional Transceiver

Advance in integrated circuit technologies requires in support of the high-performance I/O buffer, However the I/O buffer bandwidth has increased less rapidly. Simultaneous bidirectional transceiver logic (SBTL), which is proposed to cover the chip transmission bottleneck, is using an I/O pin simultaneous sending and receiving signals, will effectively double the data bandwidth increase.Based on a systematic study of various international SBTL technologies, we have designed a high-performance SBTL buffer and completed the layout design and verification.According to the nature of transmission line and reflection theory, the perfect impedance match of output buffer and transmission line is necessory for SBTL signaling. But the MOS channel resistance in CMOS process is influenced by process and temperature badly. This paper describes the design of a variable impedance output buffer, and its adaptive control circuit. It can automatically adjust the impedance of output buffer in real-time. On this basis, a novel adaptive impedance control circuit has been designed. It can directly track the transmission line impedance, achieving beter impedance matching and saving two pads and two resistors. The SBTL system emploies pseudo-differential signal transmission technology to achieve the capacity of against common mode noise with the minimum cost. Moreover, The SBTL buffer has predistion function, which can effectively improve the ability of against SIS, and without addtional EMI and extra power costs.The chip was implemented in the 0.18μm CMOS process. The simulation shows the chip can working in 1GHz frequency and 2Gb/s of unidirectional data, 4Gb/s of bidirectional data. It also shows the average power consumption is only 18.9mW.