| The consideration of device fluctuation is an important theme in designing CMOS integrated circuits, particularly on the deep submicron technology (90 and 65 nm). In digital circuit, effect of intra-die variations on performances of circuit especially becomes important consideration in design. However, since intra-die variation is much more complex and difficult to measure than inter-die variations, until now, there is no acknowledged model to describe it comprehensively, although many works engage in this topic.; This master thesis investigates method of characterizing the effect of die-to-die and intra-die variations on propagation delays by evaluating single cell delay and delay mismatch in Ring Oscillator (RO). A test circuit is presented including its design, simulation and implementation. Single cell delay mismatch will first be introduced and typical application circuits suffering from this delay mismatch will be discussed as well. And then, the master thesis will study some knowledge relating to process variations and analyze theoretically this variation impact on performances of integrated circuits. Next, some previous works will be reviewed about process variations analysis and characterization methods with test circuits, and their possible drawbacks will be reported. After that, a proposed test architecture, which is based on modified RO, is presented. This novel test structure can be used to evaluate propagation delay and delay mismatch in RO by only measuring period (frequency) of each RO with conventional frequency measurement equipment.; The design considerations and implementation along with creating symmetrical architecture and interconnect effect in the layout are also investigated in detail in this master thesis. Both pre-layout and post-layout simulation results indicate the accuracy and the feasibility of our method. The test chip was implemented with TSMC 0.18um CMOS technology; it's easily reused for submicron technologies. The proposed technique to characterize the effect of process variations on delays can help designers to solve the problems caused by process variability in their new circuit design. |
