From uncertainty to opportunity: Joint architecture and circuit resilience to mitigate the impact of process variations

Future advanced process technologies will continue to provide transistor density and speed improvements through aggressive feature scaling and novel device topologies, which has been and will continue to be the most important driving force for the evolution of microprocessor industry. However, the road is fraught with difficulties resulting from increased process variations during chip fabrication process that limit performance gains from technology scaling and affect stability of key architecture and circuit blocks on the die. Microprocessor designers will soon be forced to design with the expectation of significant variations in transistor feature sizes and threshold voltages due to sub-wavelength lithography irregularity and random dopant fluctuations [ ]. Process variations (PV) will manifest in several different ways: through random or systematic (correlated) variations that may occur within a single die (WID: within-die variations) or across multiple dies (D2D: die-to-die variations) in a production run. Recent estimates suggest that process variability could impact performance by a full process generation and traditional frequency binning alone cannot solve the strong variation problem [ ].;While the last few years have seen an increased interest in developing statistical timing models and circuit level techniques to address variability, there has been comparably little work at higher levels of design. However, fundamental microarchitectural decisions that impact performance (e. g. selection of pipeline depth and sizing of architectural resources) have a substantial impact on the distribution of chip frequency as well as IPC (instructions-per-cycle), both of which can affect the system throughput and performance. Under strong PV, each fabricated chip has different characteristics, and therefore we argue that machines should no longer be designed with rigid, fixed configurations.;Process variations cause uncertainty in the performance of final products and impose significant design challenges. In this dissertation, we study the opportunity of using resilient circuit and architecture structures to mitigate the impact with minimal design and testing overhead. By adapting various tuning knobs we add into the design, each (hip can be configured to the best performance points according to different degrees of process variation. This fine-grained per-chip tuning solution is highly different from the existing coarse-grained solutions like frequency binning. We believe the general idea of resilient and flexible design style will become crucial to solve the increasing variation problem seen in the near future.