Verification and planning of the power delivery network in integrated circuits under design uncertainties

This thesis develops a suite of techniques to plan and verify the power delivery network in integrated circuits under design uncertainties. Such uncertainties in the design flow arise from the need to perform early-stage routing of the on-die power network and from the fact that the network includes on-die and off-die stages such as the package and motherboard. The present work builds on a systematic framework for dealing with this uncertainty, based on user-specified current constraints, with the aim of improving efficiency and enlarging the scope of capabilities handled within this framework. One contribution enables incremental verification of the on-die power grid that is useful for iterative design refinements. Another contribution proves some results on an RC-model of the power grid and explores the geometry of the feasible space for circuit activities to yield an efficient technique for the verification and early-stage prototyping of the power grid. A third contribution introduces the concept of time-frequency description of circuit currents, using wavelet analysis, and combines this description with constraints on circuit currents to formulate a framework that both computes the worst-case voltage drop for verification and constructs the worst-case stimulus for diagnostics. This wavelet-based approach can be effective in the co-design of the power delivery system such as package/die, can predict worst-cases on the power grid in localized stages (e.g. share due to package alone), and can be applied in the early-stage verification of the on-die power grid.