Analysis And Design Of Through Silicon Via-Based Power Delivery Network In 3D ICs

With the increasing difficulty of semiconductor manufacturing technology,the increasing cost of research and development,and the physical limitations of quantum effects faced by integrated circuits,the growth in performance and integration of planar integrated circuits has slowed down.Some professionals put forward a new development concept beyond Moore's law,which can improve the comprehensive performance of the system by developing new devices,new structures,and new integrated packaging technology.In the new generation of integration technology,a three-dimensional(3-D)integration technology based on through silicon via(TSV)has been rapidly developed and applied due to its novel design mode and potential advantages.This is an important development direction of microelectronics.Multi-functional 3-D integrated system can promote Moore's law to develop continuously.3-D integration enables vertical stacking of bare or packaging chips in the vertical direction.This design pattern with both manufacturing and packaging technologies enables higher integration,lower interconnection delay,faster speed and multi-functional heterogeneous integration.Although 3-D integration technology has many advantages,there are still many design constraints and reliability issues related to 3-D integration,which are the difficulties faced by the sustainable development of 3-D integration.For example,the power distribution network(PDN)model in 3-D integrated circuits(3-D ICs)has to be improved,the impact of TSV on system power integrity,the noise coupling among TSV arrays and the impact on power delivery,the thermal dissipation of TSV and PDN,and the comprehensive optimization and design of power and thermal constraints in 3-D integration.This thesis focuses on 3-D integration and power distribution network,and explores the modeling of 3-D power distribution network,impact of TSV parasitic parameters,TSV noise coupling,thermal dissipation of 3-D PDN and TSV,and comprehensive optimization of power and thermal constraints.The main work and research achievements obtained in thesis are below: 1.A compact impedance model of 3-D PDN and an optimization scheme for improving the power integrity of TSV are proposed,which can be used for analyzing impedance and power noise of 3-D integrated structures.According to the physical structure of the on-chip PDN,the PDN impedance is obtained by integration method.Combining with the cascade structure of the multilayer chip stack,a 3-D PDN impedance model is obtained.The ADS validation shows that our model has higher accuracy and computational efficiency.This model can be used to analyze the effect of TSV on the 3-D PDN impedance.The effect of parameters such as height,radius and pitch of TSV on the PDN impedance is mainly introduced.On the premise of keeping the metal area of TSV unchanged,we use several small-sized TSVs in parallel structure to replace the original large-size TSV,which can reduce the resistance and inductance and increase the capacitance of the entire TSV link,and thus effectively suppress the voltage drop and power noise induced by the TSV link.Through calculation and simulation verification,the peak noise caused by TSV can be reduced by 60%,which is of great significance for the design and optimization of 3-D PDN.2.A TSV noise coupling model for 3-D PDN is proposed.In 3-D ICs,the density of TSV is very large,and thus the electromagnetic coupling effect between TSVs is very serious.According to the arrangement of TSVs used in power distribution network,an electromagnetic coupling model based on multi-conductor transmission lines is proposed.This model can be used to calculate the S parameters in TSV array,but also can be applied to analyze the simultaneous switching noise(SSN)coupling caused by circuit operation.The simulation results of ANSYS HFSS show that the calculation error of our model is small and the computational efficiency is high.Furthermore,we analyze the effects of stacking layers,TSV density and on-chip PDN specifications on the power supply of the stack structure.By reflecting the propagation and reflection of electromagnetic waves between TSVs,this model enables us to understand the physical principle of noise coupling.It is very important for us to analyze the noise of large-scale TSV arrays and to formulate corresponding noise suppression measures.3.A numerical model for solving temperature distribution of 3-D ICs is proposed.Considering the physical properties and structure of the 3-D PDN,we focus on its heat conduction capability.In view of the difference in on-chip PDN and TSV structure,the equivalent thermal conductivity of TSV and on-chip PDN structures are modeled and calculated respectively.The effects of key parameters such as TSV pitch,thickness of oxide layer around TSV,metal pitch and number of metal layers in PDN on thermal conduction are analyzed.By embedding the results of equivalent thermal conductivities into our proposed numerical method,finite volume method(FVM),the temperature distribution of 3-D stacked structures can be solved.Through the finite element simulation validation of COMSOL,the proposed models of equivalent thermal conductivity and temperature solution have good calculation accuracy.Compared with the simulation,the proposed mathematical model has high computational efficiency and consumes less computing resources.This method can be effectively applied to analyze the temperature characteristic of large-scale integrated systems,and has a good application prospect.4.The power and temperature constraints faced by 3-D integration are studied.According to the TSV-based 3-D stack structure,we propose an optimization scheme for TSV quantity.Through the structural characteristics of grid-type PDN and the resonant cavity method,combined with the multi-ports connected by PDN and TSVs,the multi-input impedance characteristics of PDN are calculated and analyzed.This method takes the global effect on the PDN into account and has important practical application value.In view of the power delivery and heat conduction of TSV and PDN,we propose a comprehensive optimization scheme for different chip layers according to the chip stacking characteristics with different functions,which meets the whole power and temperature constraints.Moreover,some key suggestions for the chip stacking order with different power consumption in the vertical direction are put forward.Reasonable selection of chip stacking order based on different constraints can improve the reliability of the stack structure.This optimization scheme greatly reduces the required quantity of TSVs in the stack structure,and further reduces the manufacturing costs and improves the overall performance.