| Stacking multiple dies to form 3-D integrated circuits (ICs) has emerged as a promising technology to reduce interconnect delay and power, to increase device density, and to achieve heterogeneous integration. Through-silicon vias (TSVs), metallic wires that connect different dies, are a key enabling technology for 3-D ICs. TSVs can be used for routing signals, for power delivery, and for heat extraction. TSV-manufacturing advances are well underway. However, there is little experience in designing optimally with TSVs.;This thesis explores challenges and best design strategies for TSVs, and offers several key contributions. Signal TSVs induce noise in the substrate and affect neighboring devices. This thesis proposes a novel technique, GND Plug, to mitigate TSV-induced noise. The results show the superiority of this technique in grounding noise compared to other techniques adapted from 2-D planar technologies such as a backside ground plane and traditional substrate contacts. The thesis also investigates in the form of a comparative study the impact of TSV size and granularity, spacing of controlled collapsed chip connections (C4) connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The thesis provides detailed "best design" practices for designing 3-D power delivery networks. TSVs occupy silicon real-estate and impact device density. This thesis provides four algorithms, in an iterative framework, to minimize the number of TSVs needed for power delivery network. Unlike prior work, these algorithms can be applied early in the design stages when only functional block-level behaviors and a floorplan are available. Finally, the thesis explores using Carbon Nanotubes to design the TSVs and power grid, and the results show that the use of Carbon Nanotubes for grid design offers substantial advantages in terms of reducing IR drops. Overall, the thesis advances the state-of-art in 3-D design. |
