Integrated circuits switching current modeling, measurement and power delivery network optimization

Switching currents on the Integrated Circuits (ICs) power distribution network (PDN) are very often the ultimate source of a system level electromagnetic interference issue. Modeling and measurement of this switching current are critical for minimizing those problems.; The first paper presented the design, fabrication and characterization of a balanced shielded miniature thin-film. The thin film probe was analytically shown to have better E-field rejection rate than a traditional simple loop probe. Application examples were given. In particular, narrow-band phase extraction at harmonic frequencies was presented.; The second paper investigated the coupling from IC unbalanced switching current to the TEM cell. The cause of the asymmetrical current was studied. The theory was applied to a test chip to demonstrate that TEM cell emission could be reduced by balancing power distribution network impedance.; The third paper presented a full chip level IC PDN model to predict the switching current behavior at chip level. In particular, two switching current reduction methods were discussed. The limitations of the on-chip decoupling capacitor caused by channel resistance and power grid resistance were derived mathematically. Automatic on-chip decoupling capacitor placement optimization by Genetic Algorithms was developed. This paper suggested that the optimized package impedance could be a "cheaper" solution to reduce switching current compared to increasing on-chip decoupling capacitance without causing power integrity issue. Finally, two test chips were designed to validate the model. The experimental results support the conclusions from the IC PDN model.