A hybrid instruction set simulator for system level design

Validation is an essential step in System Level Design (SLD) for Multiprocessor System on Chip (MPSoC). Traditional Instruction Set Simulators (ISS) are often either slow (interpretive ISS) or unable to handle accurate multiprocessor simulation (static or dynamically compiled ISS). In this thesis, we propose a hybrid simulation scheme which combines interpreted and static compiled ISS. The proposed ISS is free to execute a target function either natively or in interpreted mode. With the aid of System Level Description Languages (SLDL) like SpecC/SystemC, the designer using proposed ISS is able to differentiate the computation portion and the communication portion of the target code. By executing the computation intensive code on the host natively and the communication portion in interpreted mode, the proposed ISS is able to speed up the simulation significantly while maintaining acceptable accuracy and support for multiprocessor simulation. We have implemented the proposed scheme based on SWARM [6] [13] [11] simulator and have conducted experiments with several real-life designs. Our test results show that the proposed ISS provides significant speedup in simulation time and maintains low error in timing estimation.