| The demand for high-capacity, low-power memory is increasing rapidly as modern portable electronic devices boost performance while decreasing in size. Due to its many advantages over tradition floating gate memory, SONOS-type nonvolatile semiconductor memories and their various derivative seems to be the next step in the evolution of NVSM technology. Its simple structure, compatibility with CMOS technology, low power dissipation, and radiation hardness make SONOS an attractive alternative to floating gate NVSM technology. The incorporation of high-K dielectrics such as Al2O3 for the blocking insulator further improves the performance of SONOS-type charge trapping memory devices.;We have used various electrical characterization techniques to study these types of devices and gain an understanding of the physical processes governing their operation. A charge transport model has been developed to simulate the write/erase speed of SONOS, SANOS, and MANOS devices, and excellent correlation with experimental results has been achieved. A method for determining the location of the charge centroid in charge trapping memory devices has also been developed and demonstrated with SONOS and MANOS NVSMs.;Methods for optimizing the gate stack of charge trapping NVSM devices are also examined in this thesis. The performance of silicon-rich and stoichiometric nitride layers are compared, as well as multi-layer nitrides composed of a mixture of the two types. Stoichiometric silicon nitride (Si3N 4) is shown to improve retention in MANOS devices without sacrificing programming speed.;Charge trapping memory capacitors on a gridded substrate have also been designed, and an automated flatband voltage tracking system has been developed to characterize them. The gridded substrate provides a source of free minority carriers for advanced electrical characterization techniques that normally would require transistors, greatly reducing the fabrication time needed for gate stack optimization studies. |
