Studies On The Effects Of The Interface And The Energy-band Alignment On The Performance Of The Charge-trapping Memory Devices

SONOS(Si/SiO2/Si3N4/SiO2/poly-Si)type charge-trapping memory(CTM)has many advantages,such as fast program/erase speed,low power consumption,good retention property and excellent compatibility with CMOS process.It has been widely used in cellphones,computers,cameras and some electronics area.As a charge trap layer(CTL),high-k materials,closely matched with the conduction band potential of channel and replacing the Si3N4 in SONOS,were chosen to improve retention characteristic.On account of good thermal stability and high dielectric constant,Al2O3 was usually employed as tunneling layer and blocking layer.But the higher density of interfacial states at the interface between Al2O3 and p-Si would trap charge and lead to a bad retention performance.In order to solve this problem,inserting SiO2layer at the interface p-Si/Al2O3could reduce interfacial states.The curves in that the flat band voltage offset varying with time can be obtained by using traditional measuring methods for the retention characteristic of the memory device.However,microwave impedance microscopy,by which the variation of devices'conductivity along vertical dimension with the image format after programing or erasing operation could be observed,provided a visible measuring method to characterize retention characteristic.In this dissertation,we studied the effects of different energy-band alignment of CTM and SiO2buffer layer at the interface p-Si/Al2O3on the memory performance of high-k composite dielectric CTM.Besides,we attempted to employe a method to chanracterize the retention property visibly by using microwave impedance microscopy.1.Based on(Al2O3)x(TiO2)1-x(x=0.or 0.4)as the CTL,the memory structure of p-Si/Al2O3/(Al2O3)x(TiO2)i-x/A12O3/Pt was fabricated.Due to(A12O3)o.3(TiO2)0.7 as the CTL,a large memory window could be obtained,which was ascribed to the high dielectric constant and high proportion of TiO2.According to the energy-band alignment matching theory model,we calculated the band gap,the potential of the conduction-band minimum(CBM)and the valance-band maximum(VBM)in different stoichiometric(Al2O3)x(TiO2)1-x CTL.The results show that the potential of the CBM of(Al2O3)x(TiO2)1-x decreased with the increase of the proportion of TiO2.When the conduction-band minimum of the CTL was less than that of p-Si conduction-band minimum,electrons would tunnel spontaneously from p-Si toward the CTL.Hence the flat band voltage offset after programing operation will become larger with time.Due to the closely matching conduction-band minimum of(Al2O3)o.4(TiO2)o.6with that of p-Si,the corresponding device showed a better retention characteristic.2.SiO2layer was inserted between p-Si and Al2O3.Compared with the decvices with pure Al2O3tunneling layer,the devices with SiO2layer showed a smaller memory window but a good retention characteristic due to the fact that inserting SiO2 layer reduced the interfacial states at A12O3/p-Si interface.3.Ta2O5 and(ZnO)0.75(Ta2O5)0.25were chosen as the CTL to fabricated the charge-trapping memory devices,respectively.After erasing operation,the flat band voltage offset in the retention characteristic of two devices decreased.However,for the device including(ZnO)0.75(Ta2O5)o.25,the flat band voltage offset of its retention curves increased gradually after programing operation.This phenomenon was attributed to the spontaneous election tunneling behavior.Besides,the retention characteristic was also characterized by using microwave impedance microscopy.The result can be visualised directly and it was consistent with the result obtained by using the traditional characterization method.