Multicore processing engines for machine vision, image analysis and data compression

Availability of complex programmable logic units such as Field Programmable Gate Arrays (FPGAs), advanced CAD tools for hardware/software partitioning and streamlined integration of sensor arrays with System-on-Chip (SoC) components provide a remarkable potential for a new generation of embedded systems which are adaptable, fast, compact, low power and easy to develop. In particular, architectures based on multi-core processing engines can offer the computational power and flexibility to applications in diverse fields such as machine vision, image analysis, and data compression. Consequently, in this research, we aim to address the increased computational demands of real-time sensor array applications by developing efficient algorithms and parallel architectures for hardware synthesis. A significant contribution of this work is the development of a common framework which is based on hardware accelerators and software processor(s) synthesized within a single SoC. This framework establishes reusable components in sensor applications such as video processing and dramatically reduces the development time.;First, we analyze the compression of ultrasonic data using the wavelet transform. Designing universal embedded hardware architecture for Discrete Wavelet Transform (DWT) is a challenging problem due to the diversity among wavelet kernel filters. We present three different hardware architectures for implementing multiple wavelet kernels. We analyze efficient volumetric ultrasonic data compression algorithms which require fewer computations and can be implemented with fewer hardware resources. DWT is used for compression of 3D ultrasonic data. Different wavelet kernels are analyzed and benchmarked for compression of experimental signals. In order to reduce computational complexity, non-uniform DWT method is utilized where different wavelet filters are applied to ultrasonic axial resolution and spatial resolutions.;FPGA-based design and implementation of a high-performance image and video processing platform is presented. A hardware/software codesign system is proposed to realize complex algorithms for real-time image and video processing applications.;Finally, we present the implementation of HTTP and FTP servers on FPGAs. This allows the control over internet of any proposed processing platform. Any data can be retrieved and stored on a host computer instead of using the limited amount of resources available on the FPGA.