Data Compression Algorithm

The applications of lossless data compression spread widely in communication, spaceflight, medical treatment and some other fields. Now the compression implementation realized by VLSI technology is getting more and more sights due to its more powerful processing ability. And the research on VLSI compression technology is becoming hot.This thesis mainly deals with the design and implementation of a lossless data compression core in hardware. The compression core is based on LZW algorithm. The thesis raises a special architecture of the lossless data compression core according to characteristic of the LZW algorithm. This architecture uses a parallel dictionary searching strategy which speeds up the string searching in dictionary quitely. Meanwhile, a big dictionary is split into 8 dictionaries with different size, which saves the memory space and reduces the chip area. A simulation model, which is used to prove the correctness of the function, is designed with C++ based on the architecture. Then the compression core is divided to module level and every module is described with RTL language (Verilog). In the design of the dictionary module, it use a hierarchical design methodology which make the dictionary design quite clear and save much coding effort. The configurable control register module is designed to control various function of the compression core. These configurable registers make the control subsystem and data processing subsystem apart and also is helpful for the extension of the function. The design of the compression core reflects the DFT thinking. It designs a logic BIST structure which based on the CRC16 checker. This logic BIST can help the function test at full speed.After the design of the compress core is finished, the simulation environment, which is based on the VCS simulator, is established. The design of the compression core is simulated in the simulation environment. The simulation result reveals that the compression core can compress data correctly according to the LZW algorithm. The Synplify tool is used to synthesis the RTL code of the compression core, Xilinx Virtex4 FPGA as the target FPGA. The synthesis result reveals that the resource is acceptable, the maximum frequency is 210MHz. So the total data processing ability reaches to 750Mbps, which is twenty times larger than software implementation and can compare to the other hardware compression core in market.