Fast Algorithm Research And Hardware Implementation On Image Processing

Digital image has become an important aspect of people’s daily life with the development of science and technology in the area of intelligent image recognition, information security, industrial control, medical, areospace and so on. Image processing depends on efficient algorithms which have a wide of application. Traditionally, image processing meets the limit of high cost and low throughput for its amount of data. To solve this problem, fast image processing algorithms have been developed. With the evolution of semiconductor, it is able to integrate more elements in a single chip. Hardware research has been considered as an important approach for chip design and processing acceleration. As a result, it is practical to consider both algorithm and hardware analysis in solving the limit of image processing.Image compression, reconstruction, enhancment have been typical image processing area. Compressed sensing is a new theory in signal processing and it has a great potential application in natural and medical images. Fingerprint identification evelutioned a lot in security area for its uniqueness. It is hevily relied on fingerprint image enhancement. Besides, capturing is an important approach to acquire images. Ultrasound beamformer is such a means to capture ultrasound image. This paper mainly focus on the research on compressed sensing, fingerprint image enhancement and ultrasound beamformer. In order to design high efficient image processing system, these applications have been analized from the point of both algorithm and hardware.Basic arithmetic element functions are the fundamental of image processing, they are playing important role in realizing high efficient hardware architecture. Divide, square root and square root reciprocal are implemented in this paper for image processing. Novelty of this paper is summarized as follow.1) Common sub-express elimination based multiple linear approximations and Newton-Raphson method has been proposed to realize square root reciprocal in this paper. The combination method achieves high precision at a low resource usage, and it outperforms the Intellecture Property (IP) core provided by Altera in both precision and throughput. Besides, different iterations on the influence on divide and square root reciprocal precisions have been compared. With the comparison on hardware architecture, this paper delights some useful hardware design delight for image processing.2) Adaptive sampling and separable linear reconstruction have been proposed for compressed sensing. Compressed sensing is a new theory beyong Nyquist sampling. Since its reconstruction is computational high, this paper exploits the structure information in spatial image and the parallel processing properties to reduce the computational burden. Besides, the recontructed image quality has negligible loss.3) Time-efficient hardware architecture has been proposed for compressed sensing. For the lack of real-time processing of images, efficient hardware architecture has been presented by exploiting the parallel properties in both architecture and processing tasks. Besides, by exploiting parallel properties and pipeline technologies in basic arithmetic functions, high throughput Cholesky decomposition has been proposed. Compared to the relative research of state-of-the-art, great performance has been gained in the proposed compress sensing hardware system, which meets the real-time processing for even large size of images.4) With the methods of Coordinated Rotation Digital Computer (CORDIC) technology and iterated processing strategy, hardware architecture of fingerprint image enhancement has been proposed in this paper. Traditionally, it takes a long time to accomplish the enhancement when using software. To find the best tradeoff between speed and resource usage, the usage of bus and pulse technology offers a competitive hardware for fingerprint image enhancement. The proposed hardware gains a speedup of5times at least compared to software based approach. Moreover, it demonstrates an optimization design for both speed and resource cost.5) Extended aperture, purity harmonic and phase interpolation are combined to design a low cost and high frame rate ultrasound beamformer system. Ultrasoud beamformer is the fundanmental of ultrasound imaging, and it requires the real-time processing of amounts of channel data. Traditionally, multiple chips have been used to meet the performance requirement, which is cost high. However, the proposed approach can solve this issue. It can realize64effective channels with32active channels. Besides, great flexibility has gained with dynamic configuration.