Ultra-low power wideband frequency synthesis techniques

Ultra-low power wideband frequency synthesis technique is investigated in this research. It covers some issues related to the voltage-controlled oscillators (VCO) and phase-locked loop (PLL) based frequency synthesizer design. The importance of VCO control-linearity is emphasized. Constant gain of the VCO is tightly related to the phase-locked loop stability, monotonicity of loop-gain and loop settling-time as it plays an important role in the loop transfer function. This dissertation presents a novel linearization technique that can be applicable to every type of oscillator. A novel switched-capacitor frequency-detector and a negative-impedance converter fulfill the frequency to current conversion and current-conveyer functions. A feedback loop makes an input current equal to the current generated from the frequency-detector by adjusting the supply voltage of the ring oscillator through a transimpedance amplifier. Once the loop reaches static state, it satisfies equation I=CVf, where C is the switched-capacitor in the frequency-detector, V is the charging voltage and f is the oscillation frequency. A linear current-controlled oscillator (CCO) is designed, simulated, fabricated and tested. The CCO has 0.12% nonlinearity at a wide tuning range of 140 MHz to 1.1 GHz in TSMC 0.18 microm CMOS technology. A method of improving the settling-time by a simple circuit-modification of the frequency-detector is discussed with supporting simulation results. It does not use negative impedance converter (NIC) and an additional current-source is added in one port with the reference voltage. Three switched-capacitors are used and driven by the three outputs from the ring oscillator with different phases. It works at a higher frequency range of 2.1 GHz to 3.3 GHz and the settling time is only 5 ns with a maximum power consumption of 3.99 mW.;A simple frequency-locked loop is presented based on the linear CCO. FLL can be used in a PLL to improve the acquisition time without affecting the loop bandwidth of the PLL. This simple FLL does not add complexity to the PLL design and the power consumption is also minimized. It is fabricated using TSMC 0.18 microm CMOS technology and has a tracking range from 100 MHz to 600 MHz with less than 2 mW power consumption under 1.8 V supply. The settling time is less than 120 ns. The proposed FLL is suitable for low-power and wide-band cognitive radio application.;An ultra-low power integer-N PLL based frequency synthesizer for MICS band transceiver is presented. The system-level loop is analyzed and simulated. Each block is studied, compared with existing work and improved for low power consumption. The system post-layout simulation shows 251 microW power consumption with a 1.2 V supply in IBM 90nm process. The simulation results meet the low power requirement of implanted devices with battery supply.;The research work presented and discussed in the thesis meets the requirements of today's wireless communication systems that are wide band, low-cost, low-power, small area and high integration.