Research On Efficient Layout Planning Scheme Based On Estimated Violations

With the rapid development of the integrated circuit industry,the scale of digital IC is getting larger,the floorplan structure is becoming more and more complex,and the design difficulty is also increasing.The quality of the floorplan directly affects the quality of the subsequent process of the chip,and then affects the final performance of the chip.As more and more modules are included in the chip,the floorplan has a long design time,and the time consumed can account for 30% of the entire physical design process.There are three main reasons for this: 1.The timing vio between the macro cells will be difficult to solve.Designers need to solve it by repeatedly modifying the spacing between the macro cells.2.There will be multiple violations at the corners of irregularly shaped block.Because traditional methods cannot effectively solve the violations at the corners,designers cannot fully estimate the violations.3.Macro placement requires a lot of calculations,many iterations,and takes a long time.This article proposes three new solutions to the above three problems:1.Based on an MCU chip,this paper proposes a solution for placing back-to-back macro.The chip uses the SMIC 40 nm process,160,000 gates,and the core area is 1100um×1100um.Under this process,the standard cell power is located on the second layer,the power planning is complex,and the density between macro cells is large,which makes timing violations difficult to estimate.Compared with the traditional method,the new solution can eliminate timing violations between macro cells and reduce power consumption by 19.5%.2.Based on an L-shaped block,a solution is proposed to add Partial placement blockage on the higher side of Density by estimating the density.The block uses the TSMC 130 nm process,200,000 gates,and does not include macro cells.A large number of standard cells will generate a large number of difficult violations around the corner.With the new solution,the congestion around the corner is basically resolved.3.Based on the above research,participated in the design of a Beidou satellite baseband chip,and further studied the constraints of automatic placement of macro.The chip uses the Global Foundry 55 nm process and contains 144 macro cells with about 15 million gates.Based on Cadence’s Innovus software,two constraints were written to implement automatic placement of the macrocells.The placement results were compared with the previously completed Floorplan.By comparison,the automatic placement achieved by the two new constraints saves about 80% of the time compared with manual placement,reduces power consumption by about 5% and 3.3%,and distributes clock tree nodes more densely.