Modern Fpga Placement Study

Placement is an intermediate step between packing and routing,and has great impact on the final routability and timing closure.Routability is an important metrics of FPGA system,and is related to timing in some way.One work of this thesis is to develop a fast FPGA placer which could deal with macro blocks as well as single blocks simultaneously is proposed.The new placer takes advantage of an analytical method to figure out the ideal positions of all the blocks firstly,and then adjusts the positions of the blocks by local expansion.Finally, the typical simulated annealing algorithm is used to refine the placement at a low temperature.We also discuss how to implement a practical placer for modern FPGAs with heterogeneous resources.We divide the heterogeneous resources of FPGAs into different logic layers,obtain a fairish initial placement by quadratic method mentioned above and then employ a low-temperature simulated annealing on each logic layer to determine the final location for all modules.Experiment result shows that the algorithm is not only more efficient than the classical approach of VPR while having the same performance,but also has high-adaptability to the hierarchical modern FPGAs.Finally,timing information has a great impact on the performance of circuits,so it is one of the most important goals of EDA tools.Timing-driven placement could play a vital role to reduce the delay on critical path.We discuss some fundermental methods of timing driven placement of FPGA.