Research On Fast DRC Violation Prediction Algorithm Based On Machine Learning In Physical Design

With the dramatic shrink of IC feature size,interconnect delay has exceeded gate delay,which has become the dominant factor of the overall performance of a circuit in VLSI technology.Detailed routing has become one of the most challenging and time-consuming stages of the physical design process.A good routability estimation method is needed in the early design stages,which has become one of the popular research fields.Global routing congestion map is used by general commercial APR tools to predict DRC violation for estimating routability.However,more complex design rules are introduced into physical design due to the decline in process nodes,resulting in lack of correlation between global routing congestion and detailed routing DRC violations.The placement driven by GR congestion map may leave too many DRC violations to be repaired by engineers,leading to a waste of time and resources.In this thesis,a machine learning framework is proposed to predict DRC violations aiming at the mismatch of GR congestion map and DRC violations after DR in physical design.We transform the original problem into a classification problem of the target Gcell,and use machine learning to extract layout features in the earlier stages of physical design and train models to predict DRC violations.Many layouts are generated by using open-source tool to carry out multiple placement on same circuit before the model construction to achieve data increment and make up for the insufficient training data.The codes of the open-source tool are easy to modify and adjust parameters.In addition,considering that the no-DRV-Gcell samples(negative samples)occupy a large proportion of all samples,a specialized down-sampling technique is proposed to help the model to select important samples from training dataset to solve the impact of extremely imbalanced data.The technique not only speeds up model training but also significantly improves the prediction accuracy.A new feature extraction method is proposed in this thesis.On the on hand,the method focuses on the description of routing resources at low metal layers,especially pin accessibility according to pin density and pin distribution.On the other hand,RUDY and TR/GR congestion map are used to describe nets and routing tracks.The experimental results on the two cross-validation demonstrate that,the feature extraction method can make the prediction model achieve higher accuracy compared with other methods.In this thesis,SVM-based and CNN-based DRC violations prediction models are constructed.The model based on SVM uses C-SVC as classification algorithm.We deal with the original feature data before training model,and propose a feature vector that best represents actual characteristics of layout by feature ordering and selection.In CNN-based model,a 12-layer CNN structure is proposed,which uses residual network and grouped convolution structure,and the model uses focal loss as the loss function to enhance the ability of model to classify minority samples(positive samples).The experimental results show that the above two prediction models can respectively increase the F1-score of the GR congestion map to 3times and more than 5 times.Compared with the SVM model,the CNN model requires a larger training dataset.Although the prediction accuracy results obtained by two models in this thesis are different,they have their own usage scenarios in actual projects.