Design Of NAND Flash Controller Compatible With ONFI And Toggle Mode

With the market expansion of smart phones,tablet PCs, and SSD devices,the demandfor large-capacity and high-speed storage is growing rapidly.NAND Flash as a nonvolatilememory,provides high cell densities,higher write and erase speed,low lost and longlifetime.NAND Flash memory has already become one of the most popular storagemedium.So,It has an important value to research NAND Flash controller,which isresponsible for complete the data transfer between NAND Flash chips and externaldevices.The design quality of controller affects the whole storage system’s performance.To tell the difference from the general NAND Flash controller, This paper proposes anew controller which can support the asynchronous and source synchronous interface ofONFI1.0~2.2standard,and Toggle DDR1.0interface.It has a special physical layer circuitto generate the high-speed DDR interface timing,and enhance the maximum transfer speedof NAND Flash chips.To meet the design requirements of SoC,the NAND Flash controller uses AHBinterface,which is currently the most popular SoC system bus.Its has DMA module tomove data from external devices independently,reduces CPU workload and and furtheraccelerates the data transfer speed.The data may appear bit-inverted during NAND Flash storage process,so the NANDFlash controller adds the ECC function for error detection and correction. ECC moduleuses IP core,based on BCH algorithm which can correct32-bit random errors in1K bytes.Finally, do the function simulation for the NAND Flash controller. The results showthat the design of NAND Flash controller meets the ONFI and Toggle standard timingrequirements and implements a variety of NAND Flash operation.Then,do logic synthesisand place and route with SMIC0.13library cell,Use Synopsys’ PrimeTime to finish statictiming analysis and optimization, fixing the setup and hold time violations.