Research On Key Technology For NAND Flash-Based Solid State Drive

Nearly half a century,along with the development of computer architecture and chip technology,the gap between the CPU performance and IO performance continues expanding.The performance bottleneck of a computer system is the hard disk.Although the capacity of hard disk has a great improvement,the mechanical rotating structure makes access speed limited.Compared to the traditional hard drive,solid-state drive presents much good performance,e.g.,low power consumption,excellent performance of read and write,shock resistance,no noise and light weight.Therefore,in many areas SSD has already begun to replace traditional hard disk,e.g.,high-end laptops and enterprise-level storage systems.However,SSD also suffers from several noteworthy drawbacks arising from the physical nature of NAND flash,e.g.,the inability to modify data in-place,read/write performance asymmetry,and limited erase functionality.This paper mainly studies the buffer management design and FTL design to decrease the number of write and erase operation of SSD.In the study of buffer management design,we propose a novel Virtual-Block-based Buffer Management Scheme(VBBMS),which can make full use of both temporal and spatial localities at virtual block-level.VBBMS divides RAM into random request service region,which is responsible for handling random requests,and sequential request service region,which is responsible for handling sequential requests.When replacement happens,VBBMS selects victim virtual block according to simple LRU policy in the random request service region and simple FIFO policy in the sequential request service region.VBBMS has been extensively evaluated under various realistic workloads,and our benchmark results show that VBBMS makes 20.92%,29.33%,and 44.16% improvement in terms of buffer hit ratio compared to BPLRU,CFLRU,and page-based LRU;makes 23.93%,28.09%,and 33.70% improvement in terms of average response time compared to BPLRU,CFLRU,and page-based LRU;makes 13.38%,48.77%,and 55.75% improvement in terms of erase counts compared to BPLRU,CFLRU,and page-based LRU.In the study of FTL design,we propose a novel clustered page-level flash translation layer(CPFTL)algorithm based on classification strategy.Firstly,CPFTL divides RAM into hot cached mapping table(H-CMT),cold cached mapping table(C-CMT)and sequential cached mapping table(S-CMT),which is responsible for buffering map entries of requests with high temporal locality,low temporal locality and high spatial locality,respectively.Secondly,in order to benefit from the spatial locality of sequential requests,CPFTL prefetches multiple sequential map entries into S-CMT,and thus it can improve the response performance of sequential requests.Finally,in order to reduce the read and write overhead of translation pages,CPFTL clusters the map entries,which belong to the same translation page,in C-CMT together,and manage these clusters by LRU(least recently used)strategy.When C-CMT is full,according to the map entry number and LRU of clusters,CPFTL chooses an appropriate cluster to evict into Flash.CPFTL has been extensively evaluated under various realistic workloads.Compared to state-of-art FTL schemes such as classic DFTL and the latest SDFTL,our benchmark results show that CPFTL makes 50.59% and 9.88% improvement in terms of cache hit ratio compared to DFTL and SDFTL;makes 24.43% and 8.25% improvement in terms of average response time compared to DFTL and SDFTL;makes 82.87% and 50.62% improvement in terms of operation counts of translation pages compared to DFTL and SDFTL;makes 29.35% and 9.26% improvement in terms of erase counts compared to DFTL and SDFTL.