The Design Of High-speed Data Acquisition System Based On USB 3.0 And FPGA

With most high-speed data acquisition systems relying on powerful computers for data storage and analysis,USB 3.0 Specification has gradually become a data transmission mode used by all kinds of computer platforms due to its advantages of fast data throughput,good compatibility and ease of use while FPGA has become a frequent visitor in data acquisition systems by virtue of its powerful processing capabilities and multiple logic programming.Therefore,the data acquisition system based on USB 3.0 and FPGA has dominated the researches in recent years.In this paper,the high-speed data acquisition system based on USB 3.0 and FPGA is studied in a systematic manner with a focus on the analog-to-digital converter,sampling clock,peripheral circuits for FPGA and USB 3.0 interfaces and the digital logic design of configuration and function modules in FPGA,including filtering design and analysis of signal integrity.The system is debugged with hardware and FPGA logic function modules when the design is completed,the problems encountered during the debugging are analyzed.After the debugging,the system is tested.The main contents are as follows:First,the overall design of the system is described,including the development environment,the basis for chip selection,and the requirements for the design of the system.The design method and workflow of the system and the model of each key chip are determined.Secondly,the hardware design of the system is described,including a detailed introduction of each key chip,and the design ideas and processes of the peripheral circuits of each key chip are described in detail.Then the analysis of high-speed signal integrity is described from the perspective of PCB layout and power supply structure,and the method to adopt multi-layer board design or signal layered isolation design is proposed to reduce or avoid the negative effects of crosstalk,power integrity and electromagnetic compatibility on the system.And the overall PCB structure of the system and the PCB layout of the key circuits are described.Next,the internal logic function modules of FPGA chips are described,including how to configure and control each key chip.The methods of receiving,buffering and transmitting the sampled data are also described.Finally,the debugging method of the whole system and the problems encountered during the debugging process are described,typical problems are analyzed and their ideas and solutions are shared,and the final test of the system is described.