Research And Implementation Of Security Encryption Chip Based On ARMv6 Architecture

As the mobile Internet continues to penetrate into all walks of life,people's production lifestyle has undergone earth-shaking changes.But the problem of information security has always been in front of people.Secure encryption algorithm brings an effective solution for data security.The hardware encryption scheme is widely used because of its advantages such as fast encryption speed,less resources and strong anti-attack capability.In order to meet different application scenarios,SoC needs to integrate a variety of common security encryption algorithms and integrate high-speed interface for data transmission.This paper is based on the preliminary key technology research and verification of the project "key technology research and development and industrialization of mobile secure encryption intelligent chip".Designed a secure encryption chip,mainly to accomplish the following work and innovation:(1)The cortex-m0 processor based on ARM v6 architecture is studied.After considering performance,cost and design complexity,the basic architecture of secure encryption chip is designed.The architecture adopts AMBA3.0 bus system,integrates hardware encryption and decryption module,and insets the self-designed off-chip startup module and common peripheral interface modules such as timer,serial port,GPIO,SPI,I2 C,etc.(2)In order to meet the encryption and decryption performance requirements,a dedicated data encryption and decryption hardware unit for AES algorithm is designed to handle data safely.This paper proposes a design scheme of S box reusable reconstruction: in the round function operation of AES algorithm,128 bits of data are divided into 4 groups of 32 bits of data,a reusable S box is constructed by pipeline method,and a round function operation is completed within 4 cycles,which greatly reduces the hardware overhead.Finally,the APB Slave IP interface is customized to integrate the encryption and decryption hardware into the secure encryption chip.(3)In order to reduce the project cost as much as possible,this paper proposes a new SoC startup scheme.By designing an off-chip start-up module inside the chip,the program data stored in the off-chip SD cardis loaded into the on-chip SRAM memory,and finally the address is remapped through the software start-up code to remove the entire system from on-chip Start in SRAM memory.This solution realizes a single storage medium on-chip,which greatly reduces the cost of the chip and reduces the design complexity.Compared with the traditional on-chip ROM / Flash startup method and off-chip Flash loading method,this solution does not require Using onchip ROM or Flash IP core,the area is reduced by 20%,IO pins are reduced by 6,and the off-chip SD card also meets the requirements of software debugging and upgrading.(4)After completing RTL design with Verilog,cross simulation verification was carried out on the module level and chip level,and the hardware/software coordination verification environment and FPGA hardware prototype verification were built.The results show that the function of each module of the chip is correct and the SoC starts and executes the preset program normally.(5)Complete the physical design of the chip under the SMIC 0.11?m CMOS process,perform parasitic parameter extraction and static timing analysis on the entire chip,generate a standard delay format file for post-chip simulation verification.And through the final timing sign-off and physical verification,finally GDS data is delivered to SMIC for MPW tape-out.