The Research And Design Of AES Encryption Based On FPGA

With the application of computer and network, the world will be an era of information and network sharing. So the safety of information and network are especially important. It is only the safety network that can ensure the network work orderly, that information can not be stolen, that the network system can not be gone to pot, that the service can not be interrupted. In order to guarantee the safety of network we need ensure the network system and device are in safety, but also to ensure data security. At the moment the most effective manner of guarantee data security is encrypt the data.AES as a new generation standard of American data encryption, due to advantages of AES, such as encryption speed, high safety, it has become the international standard. So there will be a long time which researches the AES as a hot topic whether home or abroad in the future and AES will be applied to the all areas of information security. There are two methods which software realization and hardware realization implementation AES algorithm. In the beginning of AES as standard, most people would like realize it through software, because it is easier and the Technology more mature. But there are many defects in software level; experts started researching on hardware implementation. This paper was designed based on hardware implementation of AES algorithm.Firstly, the paper describes theory and structure of AES algorithm in detail. After analyzing the design principles and skills, described the implementation process of the sub modules. The major factors in the design are area and speed. So in the process of algorithm implementation the decryption module reuse the S-boxes and Mixcolumns of encryption module. The Verilog HDL has been used in the paper to describe whole algorithm. Modelsim simulator tool has been used simulation all the modules in the system. Also the Quartus II provided by Altera has been used complete the system synthesis. The result shows that AES system is achieved the design goal of expected.