Hardware Design Of The Asymmetric Encryption And Decryption Based On FFTT

Human fingerprint have biological features such as uniqueness reliability and stability, so it is widely used in identity authentication. The efficient and non-repudiation advantage of asymmetric encryption and decryption algorithm based on FFTT (Fingerprint feature Topological Transformation) make it widely used in network society where today's economic commerce and e-government are developing rapidly. But due to the increase of encryption and decryption complexity and data, the software implementation based on standard CPU and DSP software cannot meet calculate requirements of data encryption and decryption algorithm. practical application, so hardware implementation based on FPGA or ASIC can meet the requirements of encryption performance processing.In this paper, we first study on the encryption and decryption algorithm theory of fingerprint feature points topological transformation, divide the fingerprint encryption algorithm into three parts:round transformation encryption and decryption, and introduce them in detail, along with the hardware circuit design knowledge, we can determine the overall hardware circuit architecture and divide the whole circuit into five functional sub-modules, they are ram interface module, round transformation module, control module, encryption module and decryption module., besides we introduced the interface function and work schedule of each sub-module in detail. As the control center of the whole circuit, control module control each module's operation. In order to get though the work of control circuit input by external signal, we can divide the circuit into three working models, they are round transformation model, encryption model and decryption model, besides, we introduced the functions and schedule relationships of different circuits in detail. As a kind of verify language, SystemVerilog have richer grammatical structure than Verilog, it can describe 'complex verification environment and have most grammatical structures that a validation engineer needs. Follow verification methodologies of System Verilog, we set up a simple verification environment and introduce the execution environment in detail and further analysis the verification results. Finally, we download the design into DE2 development board for further test, then we can capture real-time signal by Signal-Tap II and then analyzing it.