Risc-V-Based SoC Design And Its RTOS Migration

According to a corresponding instruction set architecture,a program written in a high-level programming language can be translated into instructions by a corresponding compiler,and the instuctions can be recognized by a corresponding processor.Nowadays processors are mainly based on two instruction set architectures,x86 and ARM.The long development history has made these two architectures mature enough,but also brought some unavoidable problems.Many designers have complained about the overly complicated instruction set,expensive commercial license,and source code that cannot be modified or even visible of the x86 and ARM architecture.Under the circumstances,a new instruction set architecture,RISC-V gradually attracts designers' attention.RISC-V provides a free and open source processor implementation with a relatively short development period.Facing the software ecosystem and patent barriers of foreign chips,RISC-V is expected to become an excellent choice for China to independently develop processor chips.The paper is mainly based on the research of the reference RISC-V processor,Rocket Chip,provided by the research team of RISC-V,and implement a RISC-V-based SoC.Firstly the paper studies the front-end design of the Rocket Chip-based SoC.The physical implementation of the SoC is accomplished through logic synthesis and back-end physical design.Then the function of the SoC is initially simulated by the generated software simulator.Based on the Xilinx ARTY A7 development board,the obtained SoC is implemented with FPGA and passes the prototype verification.Finally FreeRTOS is migrated on the FPGA-based RISC-V platform.The paper can be summarized as follows:1)The Rocket Chip Generator project is studied.Analyzing the architecture of the Rocket Chip project,we builds the RISC-V gnu toolchain and obtain a RISC-V-based SoC,and then utilize the generated software simulator and a simple test program to perform functional verification.2)The physical design flow of the generated SoC is studied.Utilizing Design Compiler for logic synthesis,we convert the design from RTL to gate-level netlist,and timing check and formal verification is passed.And then we use the IC Compiler tool to complete the physical implementation of the design,and timing check,physical verification,and formal verification is passed,and we obtain the final design layout.3)The FPGA implementation of the obtained SoC is studied.Using Vivado to build and synthesize the project,we utilize Xilinx ARTY A7 development board to implement the synthesized design with FPGA,and perform the prototype verification.4)Considering that embedded software development often requires real-time operating systems to improve development efficiency,the operating system migration on the RISC-V platform is studied.Based on the source code of the FreeRTOS project,we build a demo and run it in the FPGA-based RISC-V platform.