FPGA Prototype Design And Physical Implementation Of PULPino SoC Based On RISC-V

The processor industry has flourished since the first commercial processor was introduced in the 1980 s.The ARM and X86 architectures dominate most of the processor market.However,due to its high licensing costs and historical burdens that have hampered the innovation of the processor industry,RISC-V came into being.Today,with its simple design concept,customizable extension subset and no historical baggage,it has been recognized and favored by many companies and scientific research institutions.This paper first studies the theoretical analysis of RISC-V from the basic integer instruction set,the extended instruction set and the privileged instruction set.Then,based on the RISC-V-based PULPino SoC platform,the objectives of software simulation,FPGA implementation and physical layout design are completed.In software simulation,the IP organization structure and function implementation of PULPino SoC platform are analyzed from top to bottom in terms of code structure and functional model.The functional model of the PULPino SoC platform is built on the ModelSim simulator.The kernel is configured as RISCY and supports the PULP extension and the RV32 IM instruction set.Taking the helloworld application as an example,the software level simulation and analysis are implemented,which verifies the correctness of the platform structure and function level.In terms of FPGA implementation,the PULPino SoC is based on the Xilinx clock and memory module for the PULPino SoC platform,and the timing meets the requirements.Finally,the PULPino SoC platform is implemented on the ZedBoard FPGA development board,and the data interaction between the PS part Linux system and the PL part PULPino SoC platform can be realized through SPI.In terms of physical layout design,methods and key technologies for logic synthesis and back-end design are studied.The PULPino SoC platform is logically integrated in the Design Compiler tool,which is transformed from the RTL hardware description to the gate-level netlist description and meets the timing requirements.The total power consumption is 296 mW,the total area is 25906105um2,and the gate level is ensured by formal verification.The correctness of the netlist.In the Encounter,the back-end design flow from layout planning to layout filling was completed according to the SMIC 180 nm process standard cell design rule.The physical layout of the PULPino SoC platform was designed and optimized,and the DRC test was used to meet the basic requirements such as timing closure.