Research And Design Of IoT Endpoint System-on-Chip Based On RISC-V Architecture

The Internet of Things is an important component of the new generation of the information industry.It is a major upgrade of information technology to serve human production and life more comprehensively.It has a huge application prospect and contains a trillion-level market.The IoT endpoint SoC chip,as the key component of the IoT system,has a vital impact on the security and performance of the IoT system.In recent years,our country attaches great importance to the research and development of information security and self-controllable technology in the IoT.It is of great significance to design SoC chips of IoT nodes based on the open source instruction set,hardware encryption,and CNN accelerator.The main task in this thesis is to study SoC of IoT node from three aspects: chip security,information privacy and supportability of neural network algorithm,and design SoC of IoT node based on RISC-V architecture,supporting hardware encryption and CNN accelerated computing.Based on the successful DPA attack on the lightweight cryptographic algorithm SIMON,a compact countermeasure against DPA attack of SIMON is proposed based on WDDL technology.With less resource consumption,SoC nodes in the IoT have reliable data encryption measures.Aiming at the threat of hardware trojan to the security of IoT chip,the hardware trojan detection method based on bypass analysis is studied.PCA and spectral clustering analysis method is used to realize the detection of hardware trojan circuit through circuit power,which guarantees the security of SoC chip of IoT node in the process of production and packaging.In order to meet the increasing demand of neural network computing in the IoT system,a scheme of compact CNN accelerator is proposed by using circuit reuse technology,which provides strong CNN computing capability for SoC in the IoT.Finally,through the research and design of RISC-V instruction set,processor micro-architecture,processor Cache and on-chip bus,SoC,which supports hardware encryption and CNN accelerated computing,is constructed and implemented.Based on Synopsys DC synthesis tool,the resource evaluation of DPA-resistant optimization design of compact SIMON circuit is carried out.The optimization of the circuit is completed with 70.8% redundant area consumption.Synopsys PT-PX power simulation software is used to collect circuit power.PCA and spectral clustering analysis are used to detect 0.95% hardware trojan embedded in SIMON circuit according to power data.Based on Vivado 17.2 of Xilinx,the compact CNN accelerator is implemented and evaluated.With 5717 LUTs,the CNN computing ability of Cortex-M3 core exceeds that of high-performance core Cortex-A53,and the computing ability per unit frequency reaches 6 times of Intel 7500.The verification of SoC based on RISC-V is completed on Xilinx VC707 FPGA.Compared with Cortex-M3,the running frequency of the core is increased by 42%,and the resource consumption of the core LUT is reduced by 53%.