Tag Cache Design Based On Rocket Chip

With the development of computer technology,the use of computers has penetrated into various fields,and computer security is getting more and more attention.The tagged memory architecture has great value in the field of computer security.However,the tagged memory architecture results in non-negligible runtime overhead of the programs,which hinders the practical use of the tagged memory architecture.Therefore,how to reduce the runtime overhead of programs caused by the tagged memory architecture is an important issue.Based on the Rocket Chip,a tag cache is implemented between the last-level cache and the memory controller to reduce the number of memory accesses of programs on processor with the tagged memory architecture,thereby reducing the runtime overhead of programs on the processor with tagged memory architecture in this thesis.For the design of tag cache,the following work has been accomplished in this thesis:(1)Firstly,two hierarchical compression storage methods with compression ratios of 512:1 and 512:2 are designed from the perspective of improving the tag cache hit rate.Then,combined with the cache-related design methods,it is determined that the tag cache adopts the set associative mapping strategy,PLRU replacement strategy,the write-back strategy and the serial memory access strategy.And the memory structure is designed.(2)According to the above methods and strategies,the tag cache circuits of 512:1 compression ratio and 512:2 compression ratio are designed and optimized.The circuit mainly includes the split unit,the operation generating unit,the operation executing unit,the write back unit and the like.Optimization strategies mainly includes creating empty cache lines to reduce unnecessary memory access,invaliding useless cache lines to improve space utilization of tag cache,using tag counters to reduce unnecessary access to the tag cache,performing update checks to reduce unnecessary write operations and accessing SRAM in parallel to improve the ability of the tag cache to handle multitasking.(3)When dealing with parallel write tasks,the consistency between tag tables becomes a key issue due to the existence of hierarchical compression structure in the design of tag cache.Therefore,the lock mechanism is designed to enforce the order of write operations and ensure consistency between tab tables.In the experimental part,firstly the tag cache is verified based on virtual verification platform,assembly and C language.The circuit is proven to be correct.Then the performance test is performed on the processor with tag cache of 512:1 compression ratio and the processor with tag cache of 512:2 compression ratio.The test results show that the 512:1 compression ratio is more advantageous than the 512:2 compression ratio.The tag cache of 512:1 compression ratio makes the performance of processor with tagged memory architecture is increased by more than 20% on average compared to the processor with tagged memory architecture but no tag cache and is lost less than 2% compared to the processer with non-tagged memory architecture.Finally,the logic synthesis of the processor with tag cache of 512:1 compression ratio is carried out.The result shows that the tag cache hardly causes the processor to lose frequency,but for every 16 KB of cache capacity,it causes about 5% area loss which is acceptable for a cache.In summary,the tag cache effectively reduces the runtime overhead of the programs on the processor with tagged memory architecture at an acceptable area cost.