| In recent years,wireless communication technology has developed rapidly,and wireless communication standards and modulation modes are also increasing.With the large-scale popularization of fourth-generation mobile communication systems(4G)and smart phones,the application of LTE MTC cellular Io T communication is also appearing in people's daily lives increasingly.At the same time,the development of communication technology has also brought more complicated signal modulation methods,especially LTE communication,including OFDM multi-carrier modulation technology.The requirements for transceivers with multiple modulation modes and meeting multiple standards are getting higher and higher.As one of the core components in the wireless transceiver system,the power amplifier has an unusual position in the transceiver system,and its power consumption can account for 80% of the transmitter system,which affects the performance of the entire transceiver system.It has important research significance for high performance power amplifiers.Because of the low cost and high integration of CMOS technology,this thesis presents a class AB linear power amplifier based on TSMC 65 nm CMOS LP process design.In order to achieve a certain power gain requirement,a two-stage cascade structure,including a driver stage and a power stage,is employed.Among them,the driver stage and the power stage all work in the class AB state,and the driver stage increases the driving power for the power level while ensuring that the OP1 d B is lower than the IP1 d B of the power level,and the linearity of the system after the cascade is ensured.The two-stage circuit adopts a differential structure,which can achieve sufficient output power and linearity without increasing the power supply voltage.It is also beneficial for suppressing common mode noise,strong anti-interference ability,and reducing parasitic parameters and bonding wires.Considering that the CMOS process has a low breakdown voltage,it is convenient for post-cascade design to use cascode structure to avoid transistor breakdown and improve the isolation between the input and output ports.In addition,the paper also gives the stability analysis of the power amplifier,the design of the matching network,especially the output load traction,and completes the circuit design and pre-simulation,layout design and post-simulation.The post-simulation results show that the power amplifier operates stably in the frequency range of 1880~1920MHz with the power supply voltage of 3.3V.The input reflection coefficient is S11<-10 d B and the input is well matched.The output 1d B compression point is 24 d Bm.The saturated output power is greater than 26 d Bm,and the power gain is greater than 20 d B.The power additional efficiency is 25% at output 1d B compression point and its peak efficiency is 30%.The chip area is about 1.68*0.8mm2.The power amplifier of this thesis is designed in the 4G LTE Band39 mobile communication frequency band,with good linearity and poweradded efficiency,and can be applied to the LTE MTC cellular Internet of Things field.In applications where higefficiency is required,efficiency enhancement techniques such as envelope tracking,Doherty technologdynamic biasing,etc.can be combined to improve the efficiency of the power amplifier and improve overaperformance. |
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