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Fully Integrated Cmos Rf Power Amplifier

Posted on:2013-05-25Degree:MasterType:Thesis
Country:ChinaCandidate:J FuFull Text:PDF
GTID:2248330395450958Subject:Microelectronics and Solid State Electronics
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The intense competition in wireless communication market not only urges the wireless systems with basic functions, but also demands low cost, power efficient and high reliability [1]. It is a trend integrating as many components as possible in wireless systems in an inexpensive technology, such as CMOS technologies. How-ever, the implementation of high output power, high efficiency and high linearity CMOS RF power amplifiers (PAs) remains a formidable challenge, especially in deep-nanometer technologies. Also low supply voltage, low breakdown voltage of thin gate oxide in devices and high silicon substrate loss deteriorate it.The use of OFDM modulation in WLAN, enlarges the system capacity and improves their per-formance, while suffering from high peak-to-average power ratio, which requires PA operating much more linear and higher output power for sufficient power back-off.The thesis focuses on the design of a fully integrated CMOS PA for2.4GHz IEEE WLAN802.11g wireless communication systems. Firstly, impedance trans-formation network based on on-chip transformer is analyzed in details, and a par-allel power combiner (PCT) is introduced for high output power. Then, efficiency degradation effects of power combiner with partially diabled branches are quantita-tively analyzed. By disabling sub-cells for low power mode without reverse coupling, the overall efficiency is optimized. By utilizing the property that gate capacitances of PMOS and NMOS transistors vary inversely with gate-source voltage, placing a PMOS device alongside the input NMOS device minimizes AM-PM distortion. A parallel class A&B structure is presented where at high power levels, the gain expansion characteristic in class B amplifier compensates gain compression in class A, thus improving AM-AM distortion. Finally, the stability and design procedure of PA are also studied while output stage power transistors design is presented.The PA is fabricated in a standard65nrn CMOS process. The PA exhibits a21dBm maximum output power with a20dB power gain under a2.5V supply voltage. With IEEE802.11g WLAN OFDM64-QAM modulated signal applied. EVM is-25dB at the power of15bdBm. Thus, this dissertation provides some usefull guidelines for future commercial CMOS PAs design in wireless communications.
Keywords/Search Tags:CMOS, power combiner, power amplifier, linearity, efficiency
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