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Design Of 2.45GHz Power Amplifier Based On 0.28?m SOI CMOS Process

Posted on:2020-02-06Degree:MasterType:Thesis
Country:ChinaCandidate:Y P BaoFull Text:PDF
GTID:2428330626450805Subject:Engineering
Abstract/Summary:PDF Full Text Request
With the development of wireless radio transceiver technology,wireless sensor network(WSN)composed of RF sensor nodes has been widely used in environmental monitoring,smart home,Internet of things and other fields,generating huge economic benefits and continuously improving human beings Quality of life,power amplifier(PA)as an important module in the wireless communication system,located at the back end of the RF transmitter,used to amplify the power of the RF signal,is the module that consumes the most power in the RF transceiver system,reducing power consumption can Effectively improving the service life of the node battery and extending the use time of the sensor node are essential for improving the overall performance of the wireless sensor network system.Therefore,it is important to design and implement a low power consumption and high linearity power amplifier.This paper uses 0.28?m SOI CMOS process to design a 2.4~2.4835 GHz high linear power amplifier for WSN systems.Through consideration of various indicators,the overall circuit includes an input matching circuit,a driver stage circuit,an inter-stage matching circuit,a power stage circuit,and an input matching circuit.The driver stage circuit is a common-gate structure that provides a certain amount of gain for the RF input signal and selects the appropriate transistor trans-conductance for input matching.The power stage circuit is mainly used for power amplification.Its structure is cascode.The common source transistor uses a parallel structure of two transistors biased between Class A and Class AB to improve linearity.The power stage circuit adopts a structure in which three branches are connected in parallel,and the power gain and the output power are controlled by controlling the on/off of each branch by the switching voltage.The circuit has seven power gain positions.The paper carried out circuit design,pre-simulation,layout design and post-simulation.The simulation results show that the driver stage power supply voltage is 1V,the power stage power supply voltage is 1.8V,and the process angle is TT temperature is 27?,the power gain variation in the frequency range at 2.4~2.4835 GHz is small.At the 2.45 GHz frequency,the power amplifier has a small signal power gain of 22.5dB,an OP1 dB of 12.8dBm,a saturated output power of more than 16 dBm,and an efficiency of21.3% at a 1dB compression point.The power amplifier performance designed in this paper meets the design specifications and can be applied to the WSN RF transceiver chip.
Keywords/Search Tags:Power Amplifier, High Linearity, SOI CMOS, Class A, Class AB, WSN Node
PDF Full Text Request
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