3.45GHz RF Power Amplifier Design Based On The 0.28 ?m SOI CMOS Process

Power amplifiers(PA)are typically located at the last stage of the RF transmitter and are connected directly to the antenna.The carrier signal is transmitted to the input end of the power amplifier,which amplifies it,and then transmitted to the antenna,which transmits it.With the development of wireless communication technology,the demand of channel capacity is increasing and transmission rate is required.In order to prevent the distortion of the power amplifier in the process of amplifying the signal,it is required that the designed power amplifier has good linearity.In the communication system,the power amplifier itself is a very nonlinear module.Therefore,the performance of the power amplifier plays a decisive role in the performance of the whole system.Therefore,the design of high-performance power amplifier has become the core of RF circuit design.This paper uses a 0.28?m SOI CMOS process to design a 3.3~3.6GHz high linearity power amplifier for RF communication systems.In order to obtain high output power,a high power supply voltage is used.In order not to be limited to the breakdown voltage of the transistor,four stacked MOS transistors are used as the power amplifier core circuit structure designed herein.The bias of the power amplifier core circuit is a resistor divider structure A grounding capacitor is connected in parallel with the gate of each common gate in the stacked MOS transistors,so that the core circuit has an AC signal in the AC state,thereby reducing the drain gate voltage swing of the MOS transistor to avoid breakdown.A two-stage L-type matching network and a resistor-loss matching network are used as input matching networks to overcome the difficulty of high-frequency matching.The output matching network is designed using load traction technology.The paper carried out circuit design,pre-simulation,layout design and post-simulation.In the operating voltage range of 6.5V,3.3~3.6GHz,the temperature is between-40 to 85°C,the output 1dB compression point is 21.3dBm,the power gain is 13.9dB,and the power added efficiency is the most at 1dB compression point.The difference is 15.2%.The power amplifier designed in this paper meets the design specifications and can be applied to the RF communication system after being verified by the chip.