Circuit Design And Optimization For Key Operator Of Block Encryption Algorithm

With the rapid development of science and technology such as communication networks and e-commerce,the security of information has received more and more attention.At present,the information security mechanism is implemented mainly by data encryption technology.Block encryption is one of the commonly used encryption techniques.A coarse-grained reconfigurable computing platform combines the flexibility of general-purpose processors,the efficiency of application-specific integrated circuits(ASICs),and higher security levels.These advantages make the platform the ideal choice for implementing block cipher algorithms.Existing reconfigurable cryptographic processors suffer from a low throughput rate,and the scale of computing array has been continuously increasing.As a result,a large number of redundant units are needed.The inefficient functional units fail to meet the requirements for data encryption in the mobile payment field.This thesis focuses on improving the computation speed and functional unit utilization of the reconfigurable cryptographic architectureThis thesis optimizes the key circuits of existing PE array architecture and functional units by implementing a reconfigurable block cipher computing platform,with the aim of enhancing the utilization and throughput of functional units.The research work covers the following aspects:(1)Using PIN tool to analyze the block encryption algorithm,determining the frequency of each operation in the algorithm and the combined frequency between different operations,and analyzing the pattern,"binding",and distribution characteristics of each operation;(2)Based on the existing isomorphic PE arrays,a new heterogeneous PE array framework is obtained by optimizing the obtained algorithm features.The new framework optimizes the types and quantities of PE according to the pattern features and "binding" features of the target algorithm set,optimizes the distribution of PE according to the distribution features,and improves the utilization of functional units after the block encryption algorithm is mapped to the architecture;(3)Designing and implementing the circuits for basic operators(functional units)in the algorithm based on the operating characteristics in(1),analyzing the maximum delay path in the PE block by referring to the preliminary implementation results in order to identify the bottleneck module(i.e.,the S-Box module)that affects the operation speed,and finally,optimizing the circuits of the key module to improve the throughput rate of the PE array.The PE array architecture designed in this thesis undergoes board-level functional verification on the Artix-7 FPGA platform at a clock frequency of 140 MHz.The simulation test of AES-128 and DES,two most typical block encryption algorithms,shows that the functional units of the PE array architecture see a utilization rate of 41%and 24%respectively and a throughput rate of 17.92 Gbps and 9.95 Gbps respectively.The utilization rate and throughput rate provided by the proposed architecture are 36.7%?200%and 14%?382%higher than those of Cyptor,ProDFA,and RCPA reconfigurable cryptographic architectures,respectively...