Research On Cooperative Optimization Of Coarse-grained Reconfigurable Computing Architecture And Its Mapping Algorithm

As a promising accelerator alternative for computing,Coarse-Grained Reconfigurable Architecture is more flexible than ASIC,and has higher performance than general purpose processor.CGRA is often used to accelerate compute-intensive application.Architecture optimization and efficient mapping algorithms are the research hotspots in the field of reconfigurability.Traditional research of CGRA does not consider the impact of architecture on compilation performance when designing the CGRA architecture,and traditional research of mapping algorithm neglects the need of hardware resources for the algorithm,resulting in low area and power efficiency.Aiming at this problem,this thesis which is based on the idea of software and hardware collaborative design,chooses a reasonable architecture to guide the design of the mapping algorithm,and analyzes the compilation results to guide the formulation of the architectural parameters,and finally forms a fast and efficient mapping model.The main research contents and results of this thesis are as follows:1.Explore the design space of CGRA from the perspective of efficiency.This paper focuses on the composition of CGRA,including processing units,computational arrays,interconnect networks,register files,and configuration mechanisms.It introduces the different design forms of the above components and illustrates the influences which different design has on performance and hardware costs.A CGRA architecture with good performance and high efficiency is proposed in this thesis.2.To solve the problem of existing mapping algorithm,which is timeconsuming or poor performance,this thesis proposes a fast and highperformance mapping algorithm.The algorithm uses out-degree adjustment and level adjustment techniques to support the mapping of complex data flow graphs,uses route sharing and memory-aware techniques to reduce the number of nodes in the data flow graph,thus achieving pre-mapping optimization,and combines greedy ideas and backtracking algorithm which improves the speed of mapping and guarantees a good performance of mapping.3.Design an automated CGRA modeling tool and integrate the mapping algorithm into compiler.Modeling tools can generate RTL models for CGRA infrastructure and its extensions.The compiler provides a complete CGRA loop map compilation process,including the extraction of loop kernel,the build of data flow graph,scheduling and mapping.These tools provide convenience and experimental conditions for the study of CGRA architecture and mapping algorithms.4.A comprehensive assessment of the architecture and algorithm presented in this thesis is performed.Compared to the architecture with local register file,the results show that the architecture without local register file achieves a 19% better area efficiency and a 44% higher power efficiency with the support of our mapping algorithm.Compared to REGIMap,our mapping algorithm is also 285 times faster in terms of compilation speed while achieving the same performance,which verifies that our mapping model is fast and efficient.