Optimal Design And Experimental Study Of Split-Gate VDMOS With A Buffer Layer

As the core of the power electronics field,power semiconductor devices have become increasingly important with the rapid development of emerging electronic information industries such as 5G communications,smart appliances,and autonomous driving.Power MOSFET(Metal Oxide Semiconductor Filed-effect Transistor)has become the most widely used power semiconductor device besides power integrated circuits,for the advantages such as high rated power,fast switching speed,and low driving power consumption.SG VDMOS(Split Gate Vertical Double-diffused Metal Oxide Semiconductor)as a kind of typical device that has both high-speed and low-loss characteristics in MOSFETs,has become a research hotspot in academia and industry in the development trend of miniaturization,high response speed and low power loss of power semiconductor devices in recent years.SG VDMOS introduces a zero-biased split-gate polysilicon electrode in the vertical deep trench,which not only can play the role of a buried vertical field plate to assist in depleting the drift region to reduce specific on-resistance,but also able to reduce the overlap area between gate electrode and drift region to reduce gate charge.At present,most of the SG VDMOS products still use the conventional vertical split gate structure,and its performance improvement is mainly attributed to the improvement of process capabilities,which indicates that based on the existing process capabilities,it is more meaningful to find practical design methods and manufacture usable SG VDMOS devices.The main work content and results of this project are as follows:First,the electrical characteristics research and device optimization design of the BL(Buffer Layer)-SG VDMOS are performed.The electrical characteristics of the BL-SG VDMOS device and the on-state resistance composition are analyzed,and an on-resistance model suitable for the BL-SG VDMOS device is established;Compared with the non-buffered SG VDMOS,the difference in the structure of the BL-SG VDMOS is only the buffer layer at the bottom of the deep trench.,so the drift region of the BL-SG VDMOS device can be optimized by the same method as a non-buffered SG VDMOS device,and the impact by buffer layer can be studied independently.A simple optimization design formula is obtained to guide the design of the buffer layer of the BL-SG VDMOS device.Simulation results show that the BL-SG VDMOS designed with this optimization formula has better power figure of merit than the existing researches on SG VDMOS;Based on the analysis of the problems in the structure used in the previous research,two optimization structures are proposed due to process improvement,which can control the overlap area between gate and source and the overlap area between gate and drain relatively precise.The significance of the two structures is to prevent channel interruption to a certain extent when removing excess gate polysilicon.Then the BL-SG VDMOS is experimentally studied based on the existing process.This paper briefly introduce the manufacturing process used in the experiments and analyze the effect of the multi-step thermal process on the concentration distribution of the drift region of the device;According to the purpose of the project,a detailed experimental scheme was made,and the layout-level structure including the cell area,transition area,terminal area,and metal traces are studied and designed for BL-SG VDMOS to verify the theoretical formulas,the proposed optimized structure,and the conjectures related to device layout structure by experiments;A BL-SG VDMOS with a maximum V_B of 31V and the gate charge of 2.61nC was obtained,but the specific on-resistance cannot be measured accurately;The reason that the breakdown voltage of the experimental devices is lower than the designed value is analyzed and the improvement method is proposed.