Font Size: a A A

Design And Experimental Study Of 1200v 4h-SiC Planar Mosfet

Posted on:2022-03-27Degree:MasterType:Thesis
Country:ChinaCandidate:Z F PengFull Text:PDF
GTID:2518306764479654Subject:Wireless Electronics
Abstract/Summary:PDF Full Text Request
Silicon-based power devices hace developed rapidly in the past few decades,and their products have been continuously itrated,but these devices are approaching the performance limits defined by the basic material of silicon,so a new type of semiconductor material is urgently needed to improve its overall performance.Silicon carbide(SiC)has excellent physical and chemical properties,and it is suitable for the application environment of high voltage and low power consumption,so the manufacture of Metal-Oxide-Semiconductor Field Effect Transistor(MOSFET)using SiC as the semiconductor material will achieve better performance in the field of high voltage and low power consumption.Due to the excessive saturation current density of the traditional planar SiC-MOSFET(CON-MOS)in the forward conduction,so the characteristics of the device in the short-circuit state are deteriorated,and due to the excessive capacitance and charge of gate-drain of CON-MOS,the switching characteristics of the device become worse,as well as the large forward conduction voltage drop of the body diode of CON-MOS,aiming at these problems mainly,the research on the new structure of SiC-MOSFET has been carried out in this thesis,the main work is as follows:(1)A new structure of a heterojuction diode integrated in SiC-MOSFET(HJD-MOS)is proposed,compared with the structure of CON-MOS,in forward conduction,the saturation current density of HJD-MOS is 1163 A/cm~2,a decrease of68%,a smaller saturation current density will increase the withstand time of the device in short-circuit,thereby improving the short-circuit characteristics of the device.The capacitance of gate-drain of HJD-MOS is 8.6 p F/cm~2,a decrease of 89%,and the charge of gate-drain of HJD-MOS is 23 n C/cm~2,a decrease of 88%,smaller capacitance and charge of gate-drain can effectively improve the switching performance of the device.The forward conduction voltage drop of the integrated heterojuction diode inside the HJD-MOS is only 0.5 V,a decrease of 83%,a smaller turn-on voltage drop of diode enables better on-state performance in third-quadrant of device.During the process of reverse recovery,the peak reverse recovery current of the integrated heterojuction diode inside the HJD-MOS is 47 A,a decrease of 46%,the reverse recovery time is 28 ns,a decrease of 33%,which will improve the problem of poor reverse recovery characteristics of the body diode of CON-MOS.During the process of switching,the loss of turn-on of HJD-MOS is 18 m J/cm~2,a decrease of 55%,and the loss of turn-off of HJD-MOS is 13 m J/cm~2,a decrease of 59%,the smaller switching loss will directly improve the application effiency of the device.(2)Combined with the existing domestic process platform,the biasing of the key process parameters of traditional structure was carried out,at the same time,the parameters of the devices were tested after taping-out,and the devices that failed in the reliability assessment were analyzed,therefore,based on the process of traditional structure,the subsequent process design and tape-out of the HJD-MOS will be carried out in the future.
Keywords/Search Tags:4H-SiC, MOSFET, Split gate, Shielding layer, Heterojucton diode
PDF Full Text Request
Related items