Design And Implementation Of Pci-express DMA Controller In The FPGA Hardware Accelerating System For Helical Cone-beam CT 3d Reconstruction

Since the setup of computerized tomography (CT) scanner by Hounsfield in 1972, there have been great advances in medical diagnosis and nondestructive examination. CT is an advanced medical diagnosis technology. It has a very broad application prospects. Medical CT has evolved to a new helical cone-beam orientation after the appearance of multi-slice helical cone-beam CT. The image which will be reconstructed from helical cone-beam scanner has high scan speed and space resolution. But the helical cone-beam CT reconstruction theory is complicated and it has a very large data size to compute. The implementation of helical cone-beam CT reconstruction theory is difficult, especially in computation speed. It is hard to overcome this bottleneck. This project is focus on the hardware acceleration of image reconstruction using helical cone-beam CT reconstruction theory. Our purpose is to speed up the reconstruction and raise image definition. There is a wide application prospect in market.This article implements the critical part of the HCBCT 3D reconstruction hardware accelerator, which accomplished the data transmission between CT scanner memory and hardware accelerator. This article chooses DMA mode of PCI-Express bus to accomplish the projective frame data or image data transmissions between DDR2 memory on board and memory in CT scanner. The transmission velocity meets the requirement of the hardware accelerator.This paper makes an exposition of the design scheme and goal about HCBCT 3D reconstruction hardware accelerator firstly, including system architecture and work flow. Then the function of PCI-Express DMA controller is illustrated. Considering the system requirement, the thesis analyzes the interface protocol and data format of bus transaction layer.Secondly this paper puts forward the design architecture and makes a hardware partition based on the analysis of PCI-Express protocol and DMA function. There are two difficulties in the RTL implementation. One is the PCI-Express protocol has a rule that memory transfers are never permitted to cross a 4KB boundary, so how to process the DMA requirement of successive data which cross a 4KB boundary. The other is how to write the successive projective data into disdcrete address DDR2 memory. This paper makes a detailed exposition of the solution to the above mentioned problems.At last, this paper makes an introduction to the verification environment based on Xilinx XC5VLX50T FPGA board. The verification result shows that the function of PCI-Express DMA is correct, and the performance fullfill hardware accelerator requirement. The thesis provides good conditions for the HCBCT 3D reconstruction system real-time implementation.