Design Of PXI Express Interfacing Components

PXI Express bus increases the throughput of PXI bus by adopting the PCI Express bus. And it provides new high precision timing by adding high speed differencial clocks and trigger signals, which would satisfiy quite strict requirements in certain test and measurement. In developing PXI Express equipments, there is an urgent need of PXI Express interfacing components to reduce design complexicity. In this thesis, PXI Express interfacing components are desgined that feature in high applicability and are user-friendly.Based on study of PXI Express specification, PCI Express specification and CompactPCI Express specification, the design scheme of the main part of PXI Express interfacing components, PCI Express interface, is proposed by evaluating four candidates. The selected scheme adopts high performance FPGA with embeded PCI Express hard IP core to achieve PCI Express interface. Based on the available FPGAs with required features, the low cost Cyclone IV GX-family FPGA is chosen as the interface chip.In order to achieve reusability and reducing the difficulty of integrating the interfacing components into PXI Express peripheral modules, the Qsys design flow and the network on chip system architecture are introduced into FPGA logic design. With the Qsys design flow, the hierarchical and standardize FPGA logic encapsulation becomes possible, therefore the highly reusable FPGA logic of the interfacing components can be acomplished. With Qsys flow a series of interfacing logic subsystems aimming at various applicaations are proposed. And all related IP core design are presented. In order to let secondary developer simply integrate the interfacing components with their function-specific FPGA logic without knowing the Avalon bus, a logic template is presented in the thesis.In order to verify the function and performance of the interfacing components, and further inspect the advantages of the reusable design flow, a PXI Express AD module is designed and achieved, with the PXI Express interfacing components and logic template proposed in the thesis. Based on the testing result, the PXI Express interfacing components are fully functional, with a datarate of 1.9Gbps.