Design Of High Energy Efficiency Processing In Memory SRAM For Route Matching

The rapid development of the Internet has put forward higher and higher requirements for its carrying capacity and throughput.As the key node equipment responsible for forwarding data in the Internet,the efficiency and performance of routers have also attracted more and more attention.The media used to store routing items in routers are generally assumed by Static Random Access Memory(SRAM).With the growth of routing items,the access power consumption of SRAM is increasing in the overall power consumption of routers.At the same time,the delay of SRAM limits the overall performance of routers.In order to improve the energy efficiency and performance of routing matching,a design of Processing in Memory SRAM for Hash-based routing matching is completed by using Processing in Memory(PIM)technology and fully customized design method in the TSMC 28 nm CMOS process.The capacity of SRAM is 512×64.And it supports parallel matching operation in memory while retaining the read and write function of conventional SRAM.The main work of this thesis is as follows:(1)Literature research.Three typical routing matching algorithms are summarized,and their PIM possibilities are analyzed and discussed.The existing PIM technologies are summarized,and the advantages and disadvantages of current PIM technologies are analyzed.(2)Principle and circuit design.Aiming at the high hit rate of hash routing matching,a scheme of in-memory parallel matching is proposed,which reduces the power consumption and delay of routing matching.The matching operation is embedded in SRAM and executed in parallel.The result is detected by double detection scheme of sensitive amplifier.(3)Layout realization and simulation.Layout design of the PIM SRAM is implemented in a fully customized way,and parasitic parameters are extracted from the layout to complete the post-simulation verification and analysis of power consumption and delay.The simulation results after layout show that,compared with the same capacity memory generated by traditional commercial complier,the proposed SRAM for routing matching reduces power consumption by 34.3%-50.9% and delay by 34.1%-70.1% under 0.9V conventional working voltage.However,due to the introduction of some additional circuits,the area overhead is increased by 10%.