Study Of RF Model And Parameter Extraction Of 3nm Gate-All-around FET

When the process node enters 3nm and below,with excellent gate control ability,small leakage current and effective suppression of short channel effect,gate-all-around FET(GAAFET)becomes the best choice to continue Moore's Law.Therefore,systematic research on the characteristics of GAAFET devices has important theoretical significance and application value.As the operating frequency reaches the millimeter wave frequency band,the presence of multiple parasitic effects will cause device radio frequency performance degradation,such as lower cut-off frequency and maximum oscillation frequency.At the same time,random process variations at the nanometer scale have an increasingly significant impact on transistor performance.In this paper,the RF model and process variability of GAAFET are studied.The main research contents and results are as follows:First,the physical structure of 3nm node GAAFET device is built based on TCAD.The typical DC and AC characteristics of the device is extracted through simulation,and the electrical performance of GAAFET is analyzed.Aiming at the extrinsic parasitic network of the device,the GSG layout structure corresponding to GAAFET is built based on HFSS,and it is pointed out that the traditional OPEN-SHORT de-embedding method in the millimeter wave frequency band can no longer meet the precise parameter extraction requirements.Three main sources of process fluctuations of the 3nm process generation are analyzed and pointed out:metal work function variation,channel line edge and gate edge variation.Aiming at the RF characteristics of 3nm GAAFET,this paper establishes an improved RF small-signal equivalent circuit model of intrinsic device and layout parasitic parameters,and proposes the corresponding model parameter extraction method.For intrinsic devices,based on rational function fitting,an improved two-step de-embedding simulation method is proposed to extract the intrinsic parasitic capacitance,resistance,inductance and transconductance of the device.For the external layout,the multi-step OPEN,SHORT,THRU de-embedding structure and the method of parameter extraction are optimized,so as to accurately extract the parasitic capacitance and inductance on the layout.The comparison between ADS modeling S parameters and TCAD and HFSS simulation S parameters shows that the intrinsic device model established in this paper has an error of less than 3%,the extrinsic layout model has an error of less than 1%,and the equivalent circuit model has high accuracy.Aiming at the RF characteristics of the device with process variation,this paper mainly studies the effects of metal work function,channel line edge,and gate edge variation on the GAAFET's small-signal equivalent circuit and RF performance.The research results show that the three process variations have a significant impact on the source and drain extension resistances Rgsi and Rgdi,and the maximum coefficient of variation can reach 16.50% and 16.96%.Therefore,it is particularly important for the manufacturing of advanced process nodes to control process variation and make accurate model representations.