Research And Design Of DSP Module In FPGA

With the continuous development of FPGA,its internal integrated functional modules are increasing.For example,the PCIe module is integrated to use the communication bus and interface standards to cope with the need for high-speed signal propagation.And also,the DSP module is integrated to accommodate the developer's need for computing speed.More importantly,the DSP module here is quite different from the traditional DSP chip.It discards most functions such as the instruction set,and only retains the operation logic,which makes it the computing core of the FPGA chip.FPGAs equipped with DSP modules have greatly improved the performance of computing,which makes it become the first choice for many chip manufacturers to develop.This thesis first introduces the research background of DSP modules and their components,and investigates their development process.Firstly,this thesis redesigns the adder according to the requirements of the DSP module.Based on the analysis of the existing adder,a new hybrid adder is proposed.The optimized adder adopts the tree-shaped carry structure and the carry selection structure has been used on the summation logic.secondly,this thesis introduces the existing multiplier implementation,including various super forward multipliers.After analyzing the working principle of each stage of the multiplier,this thesis optimizes the partial product compression stage of the multiplier,gives the optimization scheme of the compressor and compression algorithm,and designs a new type of compressor and compression algorithm.A new multiplier is designed.At the end of the thesis,the design scheme of the overall architecture of the DSP module is given,and the working process of the related functional mode is introduced.After the design work is completed,the function simulation scheme of the DSP module is given in this thesis,including the construction of the simulation platform and the analysis of the simulation results.Finally,the power consumption of the DSP module is modeled to evaluate the overall power consumption.Timing analysis is performed for each path of the DSP,and the strategy of area optimization and related data in the design process are also given.The topic of this thesis comes from the enterprise that cooperates with the excellent engineer of the department.The tool of function simulation of the circuit is Synopsys' VCS software,the design Compiler software used for logic synthesis and the IC Compiler software for layout and wiring,and the process is 40 nm process library of TSMC.The DSP module designed in this thesis can realize various computing functions such as multiplication,multiply and accumulate,and improve the performance of domestic FPGA chips.