An Efficient Design And Simulation Of Adder And Multiplier Based On Memristors

According to Von Neumann architecture, the conventional computer design separates the memory and the processor, which leads to"Von Neumann bottleneck". Moreover, as the processing speed and the storage capacity increase, the"Von Neumann bottleneck"dramatically limits the computer performance, which causes the"Memory Wall"issue. Meanwhile, as the CMOS size is keeping decreasing, the development of micro-electronics technology also faces the unsolvable bottleneck. As a noval technology, the memristor has many excellent electronic characteristics to tackle the above problems. The memory consisted by memristors not only has the excellent memory capability, but also has the computing capability, which can implement better combination of computing and memory. This type of memory can crack the traditional Von Neumann architecture, which is based on the separation of memory and computing.The logic computing based on memristor is totally different with the conventional computing based on CMOS circuit. The logic computing by memristor is based on the stateful logic. To this end, based on the stateful logic, we study the computing capacity of the memristors on the following three aspects:Firstly, we study the basic operations in the stateful logic for the memristor- AND operation and OR operation. AND operation and OR operation based on Implication are designed and a new customized efficient design method for AND operation and OR operation are proposed. The additional number of memristors introduced by this method is minimal. Also this method decreases the complexity of the applied voltage and reduces the errors, which makes the computing simpler and more efficient.The simulation results by SPICE show that, the efficient design method for AND operation and OR operation can correctly finish the AND and OR computing.Secondly, we present an efficient design method for the adder. In the design, the AND and OR operation are introduced. Meanwhile, we divide the memristors in adder into several areas, design the computing sequence and the applied voltage for the adder and extend the adder with a parallel fasion. Our method dramatically decreases the length of computing sequence and the complexity of the applied voltage. As a consequence, the computing reliability is increased.The simulation results by MATLAB show that, the efficient design method for the adder can correctly finish the addition operation. Finally, based on the adder, we present the design method for multiplier based on the memristor. Then, we optimize this method by adding a number of memristors, which makes the number of assignments reduced by O(n~2).