Design And Optimization Of Multiplier Circuits Within Memristive Crossbar Array

Memristor is a new type of nanoscale electronic device with high density,non-volatility,and fast reading and writing speed.Memristors play an important role in research fields such as artificial neural networks,digital logic design,and communication circuit design.Due to its ability to store and compute,the memristor has a wide range of applications in the digital logic design of non-von Neumann architecture.How to design memristor basic logic gates and memristive complex logic circuit with lower latency and area overhead to realize their precise,efficient and low-cost applications in various fields has become a hot topic of current memristor research.Aiming at the problems of high latency and area overhead in the existing memristive basic logic design due to the inability to realize multiple logic gates synchronously in one clock cycle,this thesis proposes a double majority-inverter graph utilizing the complementary resistive switching circuit structure and the nonstateful logic design method.Secondly,in view of the high latency and area overhead in the existing memristive complex logic,this thesis proposes an optimization scheme for the existing adder schemes and based on the proposed double majority-inverter graph logic,two different adders are designed for latency and area overhead respectively.Finally,a weak carry dependency multiplier is designed using the optimized adder.The main research contents of this thesis are as follows:The double majority-inverter graph logic design method is proposed.In this thesis,the circuit structure of complementary resistance switch is used to realize two basic logic gates in one clock cycle on the basis of majority-inverter graph.Through the theoretical analysis of the double majority-inverter graph logic design method,a variety of logic combinations in a single cycle and multiple cycles are designed.It mainly includes AND and NOR,NAND and OR,XOR and XNOR.On this basis,this thesis designs two different adder schemes for latency and area overhead.The proposed adders outperform the other methods compared in terms of latency and area overhead,decreased by76.47% and 75% respectively.This thesis further verifies the proposed methods using the VTEAM model,and the experimental results show the feasibility of the double majorityinverter graph logic design method.A corresponding optimization scheme is proposed for the existing toggle-cell-adder and precalculation adder,which optimized the latency and area overhead,and lays a foundation for the subsequent design of the multiplier circuit.In order to improve the parallelism of the multiplier circuit,a weak carry dependency multiplication scheme is proposed to design the multiplier circuit.And based on the hybrid CMOS/crossbar array structure with parallel capability,the circuit mapping is carried out,and the specific implementation steps of the multiplier are designed.Finally,the feasibility of the proposed multiplier is verified in the Spice simulation environment using the VTEAM model.Compared with the existing memristive multiplier circuits,the latency overhead of the proposed multiplier in this thesis is reduced to linear time complexity,and area overhead reduced by 70%.