Fpga-based High-speed Order Fir Filter Design

Along with development of the modern electrical technology, such as Radar system, image processing ,communication system, high speed and real time digital signal processing is demanded. Researchers is seeking high-speed digital signal processing algorithm to meet high-speed processing data requirement. Generally the device used for high-speed and real time digital signal processing includes ASIC, programmable digital signal processing(DSP) chipset(such as TI, AD, etc) and field programmable gates array (FPGA).In recent years, FPGA has the characteristics: flexible programmable logic which can be conveniently used to implement high-speed digital signal processing, for it break through the level limit of parallel and pipeline, reconfigurable logic resource on chip thus the resource can be utilized effectively. The researchers who engage digital signal processing are favoring FPGA . This dissertation mainly study high-speed and high-order digital FIR filter in time domain by using Xilinx Virtex II FPGA, and implement an instance of matching filter of high compression ration linear frequency modem (LFM ) pulse compression signal. The main content and work of the dissertation includes: 1. According to digital FIR filtering theory, analyze and compare the methods of designing FIR filter. 2. Parallel Distributed Arithmetic (DA) is applied to design a high-order and high-speed FIR filter in Xilinx Virtex II FPGA, detailed description and analysis is given. 3. Implement a 256-order matching filter instant of LFM compression signal, its demands: 16bits fixed input-data ,12bits fixed coefficients ,16bits fixed output-data, and 50MSPS. The designs are simulated by ModelSim software. And compare ModelSim simulated result with Matlab simulated result.