Research On Variation Considered Power Optimization Method Of Near-Threshold Circuit

With the increase of the power density and the diversity of applications,near-threshold computing is widely studied due to its energy efficiency advantages.Near-threshold computing is a promising technique to address the power bottleneck and achieve high energy efficiency,which is bound to become a new development trend of integrated circuits.However,the biggest challenge in designing near-threshold circuit design is large delay variability.Therefore,the reduction of variation is critical to exploit the potential of near-threshold computing.This thesis focuses on power optimization techniques while reducing the effect of variation.The main contributions of this thesis are described as follows.In this thesis,the sensitivity-based gate sizing method is extended,which do not consider the cell delay varation in near-threhold voltage.The statistical characteristics of cell delay is taken into consideration to form a new sensitivity fuction to meet the optimization requirements in near-threshold voltage.The optimized method can have better timing performance in the worst case without affecting the original power optimization effect.A power optimization process is constructed by analyzing the advantages and application limitations of the wave-pipelining for near-threshold circuits.In the process of constructing the wave-pipelining path,the circuit power is optimized by multi-cycle timing constraints,trigger selection,and short-path timing violation repair.At the same time,the long stage delays to can achieve greater tolerance to delay variations in ultra low voltage regime via averaging effects.The proposed methods have been verified on ISCAS89 benchmark at TSMC28 nm process and near-threshold voltage.The experiment results show that the new gate sizing method max power optimization up to 3.71% and with an average optimization of 2.69%power optimization upon the original circuit.It also has a least 3.5% timing improvement on average when compared with the original gate sizing method.The wave-pipelining based method has a max power optimization up to 13.8% and with an average optimization of 8.9%power optimization upon the original circuit.