Research On The Testing Technology Of PCI Express IP Core Embedded In Ten Million Gate Level FPGA

PCI Express is a high-speed serial computer extension bus standard,which is much better than PCI and PCI-X bus in bandwidth,operating frequency and other performance indexes.It changes from the traditional PCI's parallel bus system to the point-to-point serial bus system and takes a new step in performance scalability,known as the third-generation I/O bus for computers.With the development of FPGA toward system on chip,FPGA embedded PCI Express IP core comes into being and becomes an important logical resource in FPGA,which greatly improved the design efficiency and use efficiency of devices.This project originated from the "multi-million-gate single-particle SRAM FPGA for high-performance signal processing and high-performance logic operation" project of the institute of aerospace microelectronics technology.We systematically research the principle structure and protocol specification of PCI Express bus,studied and analyzed the existing test methods of PCI Express IP core,and designed a complete test solution for PCI Express IP core.In this paper,a test circuit based on grey box architecture is designed for the coverage test of internal resources of FPGA embedded PCI Express Gen1.1 IP core by using FPGA internal resource.This test circuit is divided into control circuit and engine circuit.Among them,the engine circuit is responsible for all kinds of packet transmitting and receiving operations that meet the protocol specification with the PCI Express IP core.The control circuit is responsible for controlling the packet transmitting and receiving behavior of the engine circuit,and analyzing the response of the PCI Express IP core to determine whether the response result is correct.On the basis of the test circuit,we design a test vector set for functional testing based on feature coverage,which reduced the design difficulty of test vectors.By optimizing the test vector set based on coverage,we get a test vector set with higher test efficiency for mass production test.At the same time,we design the test vectors needed for PCI Express IP core's signal quality testing,and constructs a special hardware test environment.The signal quality testing of PCI Express IP core transmitter(Tx)is tested from two aspects: differential swing and de-emphasis.Finally,we carry out functional simulation and board-level testing of the test circuit and test vector.The test results show that the node coverage of the internal resources in the FPGA embedded PCI Express IP core reaches 97.83%.And through the optimization of the original test vector set,the node coverage reaches 90.45% by using the optimized test vector set,and the total configuration test time is controlled in 17.5 seconds,which basically meets the requirements of engineering test.Meanwhile,the physical layer test vectors and hardware test platform designed in this paper can test the signal quality of the FPGA embedded PCI Express Gen1.1 IP core transmitter(Tx)and meet the requirements of the protocol specification.