Research And Design Of Continuous-Time Sigma-Delta Modulator

The direct conversion transceiver has been widely used in the current communication system due to it's simple structure and the characteristics of integrated easily.Its streamlined structure places higher requirements on RF front-end devices such as analog-to-digital converters.In the LTE20 communication mode,the bandwidth of the ADC will reach 20 MHz,and the accuracy also needs to exceed 12 bit.Therefore,the high-speed,high-precision ADC with high performance has become the difficulty and hot spot in the design of current RF transceiver chips.Sigma-Delta ADC can achieve a good compromise between bandwidth and accuracy and become the ideal choice in RF receiver.This paper focuses on the ADC which integrated in the RF transceiver chip.The main research contents are as follows:1.Rearch on the structure of Sigma-Delta modulatorThis paper studies the difference between continuous-time(CT)and discrete-time(DT)Sigma-Delta modulators from three aspects: working mode of feedback DAC,sampling point position and loop filter type.The CT modulator is sensitive to non-ideal factors such as excess loop delay and DAC mismatching;but its power consumption can be reduced by 75% relative to the DT modulator,and its own anti-aliasing filter effect can reduce the design difficulty and power consumption of the pre-filter.It is more suitable for intefration in RF transceiver chips.2.Modeling of Continuous-Time Sigma-Delta modulatorThe modulator needs to the accuracy of 12 bit,this paper analyzes the different implementations and selects a third-order three-bit single-loop feedback architecture for modeling and simulation based on Simulink.The results prove that the architecture meets the design requirements and leaves enough margin for the for subsequent design.The non-ideal factors are studied and processed at system level as follows: change the loop structure and add the zero-order loop which feedback to the input of the quantizer to enhance the systems' s tolerance to delay;adopts a programmable RC unit to deal with process deviations;uses a multi-bit DAC to reduce the impact of clock jitter;and adds dynamic element matching to improve the nonlinearity of the feedback DAC.3.Circuit design of Continuous-Time Sigma-Delta modulatorBased on 65 nm CMOS process,the circuit design is carried out.The integrator selects the active RC structure with the best linearity and uses the sleeve structre to reduce power consumption.The quantizer selects the Flash cascade structure to ensure the conversion rate.Feedback ADC adopts equal weight current steer structure;dynamic element matching unituses butterfly shuffling to perform first-order shaping of DAC mismatching.The previous simulation results show that the effective number of bits of the modulator is above 12 bit at any corners.4.Layout design and test of Continuous-Time Sigma-Delta modulatorThe modulator is the key node in the transition between the analog and digital parts.This paper has carefully disigned and laid out the modulation layout from the perspectives of matching and isolation.The post-simulation results show that the modulator can achieve a75.12 d B SNDR namely 12.18 bit ENOB in a 20 MHz BW and consumes only 15.5m W from a1.3V supply.The chip was taped out and test results show that the chips have normal function.Due to the superposition of RF front-end noise,the ENOB of the modulator obtained by testing is about 8.93 bit.